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Instructor: Mozafar Bag-Mohammadi Spring 2006 University of Ilam

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1 Instructor: Mozafar Bag-Mohammadi Spring 2006 University of Ilam
Chapter 5 Instructor: Mozafar Bag-Mohammadi Spring 2006 University of Ilam

2 Processor Implementation
Sequential logic design review (brief) Clock methodology (FSD) Datapath – 1 CPI Single instruction, 2’s complement, unsigned Control Multiple cycle implementation (information only) Microprogramming Exceptions

3 Review Sequential Logic
Logic is combinational if output is solely function of inputs E.g. ALU of previous lecture Logic is sequential or “has state” if output function of: Past and current inputs Past inputs remembered in “state”

4 Review Sequential Logic
Clock high, Q = D, ~Q = ~D after prop. Delay Clock low Q, ~Q remain unchanged Level-sensitive latch

5 Review Sequential Logic
E.g. Master/Slave D flip-flop While clock high, QM follows D, but QS holds At falling edge QM propagates to QS

6 Review Sequential Logic
D FF +1 Can build: Why can this fail for a latch?

7 Clocking Methology Motivation
Design data and control without considering clock Use Fully Synchronous Design (FSD) Just a convention to simplify design process Restricts design freedom Eliminates complexity, can guarantee timing correctness Not really feasible in real designs Even in this course you will violate FSD

8 Our Methodology Only flip-flops All on the same edge (e.g. falling)
All with same clock No need to draw clock signals All logic finishes in one cycle

9 Our Methodology, cont’d
No clock gating! Book has bad examples Correct design:

10 Datapath – 1 CPI Assumption: get whole instruction done in one long cycle Instructions: add, sub, and, or slt, lw, sw, & beq To do For each instruction type Putting it all together

11 Fetch Instructions Fetch instruction, then increment PC Assumes
Same for all types Assumes PC updated every cycle No branches or jumps After this instruction fetch next one

12 ALU Instructions and $1, $2, $3 # $1 <= $2 & $3 E.g. MIPS R-format
Opcode rs rt rd shamt function

13 Load/Store Instructions
lw $1, immed($2) # $1 <= M[SE(immed)+$2] E.g. MIPS I-format: Opcode rt rt immed

14 Branch Instructions beq $1, $2, addr # if ($1==$2) PC = PC + addr<<2 Actually newPC = PC + 4 target = newPC + addr << 2 # in MIPS offset from newPC if (($1 - $2) == 0) PC = target else PC = newPC

15 Branch Instructions

16 All Together

17 Control Overview Single-cycle implementation
Datapath: combinational logic, I-mem, regs, D-mem, PC Last three written at end of cycle Need control – just combinational logic! Inputs: Instruction (I-mem out) Zero (for beq) Outputs: Control lines for muxes ALUop Write-enables

18 Control Overview Fast control E.g.
Divide up work on “need to know” basis Logic with fewer inputs is faster E.g. Global control need not know which ALUop

19 ALU Control Assume ALU uses 000 and 001 or 010 add 110 sub 111
slt (set less than) others don’t care

20 ALU Control ALU-ctrl = f(opcode,function) Instruction Operation Opcode
add 000000 100000 sub 100010 and 100100 or 100101 slt 101010 ALU-ctrl = f(opcode,function)

21 But…don’t forget To simplify ALU-ctrl ALUop = f(opcode) 2 bits 6 bits
Instruction Operation Opcode function lw add 100011 xxxxxx sw 101011 beq sub 000100 100010 To simplify ALU-ctrl ALUop = f(opcode) 2 bits 6 bits

22 ALU Control ALU-ctrl = f(ALUop, function) 3 bits 2 bits 6 bits
10 add, sub, and, … 00 lw, sw 01 beq ALU-ctrl = f(ALUop, function) 3 bits 2 bits 6 bits Requires only five gates plus inverters

23 Control Signals Needed (5.19)

24 Global Control R-format: opcode rs rt rd shamt function
I-format: opcode rs rt address/immediate J-format: opcode address 6 26

25 Global Control Route instruction[25:21] as read reg1 spec
Route instruction[20:16] are read reg2 spec Route instruction[20:16] (load) and instruction[15:11] (others) to Write reg mux Call instruction[31:26] op[5:0]

26 Global Control Global control outputs ALU-ctrl - see above
ALU src - R-format, beq vs. ld/st MemRead - lw MemWrite - sw MemtoReg - lw RegDst - lw dst in bits 20:16, not 15:11 RegWrite - all but beq and sw PCSrc - beq taken

27 Global Control Global control outputs
Replace PCsrc with Branch beq PCSrc = Branch * Zero What are the inputs needed to determine above global control signals? Just Op[5:0]

28 Global Control (Fig. 5.20) RegDst = ~Op[0] ALUSrc = Op[0]
Instruction Opcode RegDst ALUSrc rrr 000000 1 lw 100011 sw 101011 x beq 000100 ??? others RegDst = ~Op[0] ALUSrc = Op[0] RegWrite = ~Op[3] * ~Op[2]

29 Global Control More complex with entire MIPS ISA Common solution: PLA
Need more systematic structure Want to share gates between control signals Common solution: PLA MIPS opcode space designed to minimize PLA inputs, minterms, and outputs See MIPS Opcode map (Fig A.19)

30 Control Signals; Add Jumps

31 Control Signals w/Jumps (5.29)

32 What’s wrong with single cycle?
Instructions Cycles Program Instruction Time Cycle (code size) X (CPI) (cycle time) Critical path probably lw: I-mem, reg-read, alu, d-mem, reg-write Other instructions faster E.g. rrr: skip d-mem Instruction variation much worse for full ISA and real implementation: FP divide Cache misses (what the heck is this? – chapter 7)

33 Single Cycle Implementation
Solution Variable clock? Too hard to control, design Fixed short clock Variable cycles per instruction

34 Multi-cycle Implementation
Clock cycle = max(i-mem,reg-read+reg-write, ALU, d-mem) Reuse combination logic on different cycles One memory One ALU without other adders But Control is more complex Need new registers to save values (e.g. IR) Used again on later cycles Logic that computes signals is reused

35 High-level Multi-cycle Data-path
Note: Instruction register, memory data register One memory with address bus One ALU with ALUOut register

36 Comment on busses Share wires to reduce #signals
Distributed multiplexor Multiple sources driving one bus Ensure only one is active!

37 Multi-cycle Ctrl Signals (Fig 5.32)

38 Multi-cycle Datapath

39 Multi-cycle Steps IR=MEM[PC] PC=PC+4 A=RF(IR[25:21]) B=RF(IR[20:16])
Description Sample Actions IF Fetch IR=MEM[PC] PC=PC+4 ID Decode A=RF(IR[25:21]) B=RF(IR[20:16]) ALUout=PC+SE(IR[15:0] << 2) EX Execute ALUout = A + SE(IR[15:0]) # lw/sw ALUout = A op B # rrr if (A==B) PC = ALUout # beq Mem Memory MEM[ALUout] = B # sw MDR = MEM[ALUout] #lw RF(IR[15:11]) = ALUout # rrr WB Writeback Reg(IR[20:16]) = MDR # lw

40 Multi-cycle Control Function of Op[5:0] and current step
Defined as Finite State Machine (FSM) or Micro-program or microcode (later) FSM – App. B State is combination of step and which path outputs Next State State Fn Output Fn Current state Inputs

41 Finite State Machine (FSM)
For each state, define: Control signals for datapath for this cycle Control signals to determine next state All instructions start in same IF state Instructions terminate by making IF next After proper PC update

42 Multi-cycle Example (and)
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB

43 Multi-cycle Example (and)

44 Nuts and Bolts--More on FSMs
You will be using FSM control for your processor implementation You will be producing the state machine and control outputs from binary (ISA/datapath controls) There are multiple methods for specifying a state machine Moore machine (output is function of state only) Mealy machine (output is function of state/input) There are different methods of assigning states

45 FSMs--State Assignment
State assignment is converting logical states to binary representation Is state assignment interesting/important? Judicious choice of state representation can make next state fcn/output fcn have fewer gates Optimal solution is hard, but having intuition is helpful (CAD tools can also help in practice)

46 State Assignment--Example
10 states in multicycle control FSM Each state can have 1 of 16 (2^4) encodings with “dense” state representation Any choice of encoding is fine functionally as long as all states are unique Appendix C-26 example: RegWrite signal

47 State Assignment, RegWrite Signal
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB State 1 State 2 State 6 State 8 State 9 State 4 State 7 State 5 State 3 State 7 (0111b) State 9 (1001b) State 4 (0100b) State 8 (1000b) Original: 2 inverters, 2 and3s, 1 or2 New: No gates--just bit 3!

48 Multi-cycle Example (lw)
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB

49 Multi-cycle Example (lw)

50 Multi-cycle Example (sw)
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB

51 Multi-cycle Example (sw)

52 Multi-cycle Example (beq T)
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB

53 Multi-cycle Example (beq T)

54 Multi-cycle Example (beq NT)

55 Multi-cycle Example (j)
PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUOp = 10 MemRead IorD = 1 MemWrite RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 MemtoReg = 1 Start ALUSrcA=0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCSrc = 00 ALUSrcA = 0 ALUSrcB = 11 ALUSrcB = 10 LW | SW RRR BEQ J LW SW IF ID EX MEM WB

56 Multi-cycle Example (j)

57 Summary Processor implementation Single cycle implementation
Datapath Control Single cycle implementation Next: microprogramming

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