1. OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads Authors : Tao Li, John, L.K. Published in : Performance, Computing, and Communications Conference, 2006. IPCCC 2006. 25th IEEE International Date of Conference : 10-12 April 2006 31 9962111, 9962306, 9962145

2. 1.Introduction 2.Experimental Methodology 3.User/OS I-Cache Accesses Characterization 4.OS-aware I-Cache Tuning 5.Power and Performance Evaluation 6.Conclusions 9962111 9962306 9962145 / 30 2 Outline

3. Dynamic power dissipation Due to charging and discharging highly capacitive bit lines and sense amps Static power dissipation -> 9962111 9962306 9962145 / 30 3 1.Introduction

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5. 9962111 9962306 9962145 / 30 5 15 app

6. Dynamic : OS-aware cache way lookup Static : OS-aware cache set drowsy mode 9962111 9962306 9962145 / 30 6

7. Modified vision of SoftWatt SimOS OS: SGI-IRI 5.3 : 8-issue superscalar processor split L1 Instruct.,data cache unified L2 cache memory 15 application 9962111 9962306 9962145 / 30 7 2.Experimental Methodology

8. Vortex : database manipulation code Gcc : compiler code Sendmail : SMTP, 1KB~1.5MB Fileman : cp, rm, chmod, tar –cvf… …… OS activity ranges from 6% in compress,92% in fileman 9962111 9962306 9962145 / 30 8 15 application

9. 9962111 9962306 9962145 / 30 9 3.User/OS I-Cache Accesses Characterization OS instruc. User instruc.

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11. A conventional 4-way set associative cache requires four tag comparisons and four data array read-outs for a cache access. Nevertheless, during user execution, performing tag comparisons and data array read-outs for OS cache lines are unnecessary and waste extra dynamic power. 9962111 9962306 9962145 11 / 30 OS-aware Cache Way Lookup

12. Cache way mode bit Processor status register(PSR) 9962111 9962306 9962145 12 / 30 OS-aware Cache Way Lookup

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14. Once generated, they remain unchanged unless a cache line replacement. The processor switches mode. 9962111 9962306 9962145 14 / 30 OS-aware Cache Way Lookup

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16. Due to CMOS technology scaling, static power due to leakage current is gaining in importance in I-cache power dissipation. These make efforts at leakage control essential to maintain control of I-cache power on current and next generations of processors. 9962111 9962306 9962145 16 / 30 OS-aware Cache Set Drowsy Mode

17. State-preserving drowsy cache techniques.(L1) Gated-V dd technique.(L2) Cache way mode bit 9962111 9962306 9962145 17 / 30 OS-aware Cache Set Drowsy Mode

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21. Access-biased classification. 9962111 9962306 9962145 21 / 30 OS-aware Cache Set Drowsy Mode

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23. OS-aware cache way lookup dynamic power user execution 29% OS execution 30% 9962111 9962306 9962145 / 30 23 5.Power and Performance Evaluation 30% dynamic power

24. dynamic power cache way access OS-aware cache way lookup 30% dynamic power power 9962111 9962306 9962145 / 30 24 5.Power and Performance Evaluation

25. Residency-based drowsy mode scheme 5% - 50% leakage power Access-based drowsy mode scheme cache drowsy state leakage power 37% leakage power 9962111 9962306 9962145 / 30 25 5.Power and Performance Evaluation

26. OS-aware cache set drowsy mode method <1% cache set drowsy mode cache set drowsy policies drowsy cache 9962111 9962306 9962145 / 30 26 5.Power and Performance Evaluation

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28. I-cache user/OS I-cache dual-mode operation 9962111 9962306 9962145 / 30 28 6.Conclusions

29. OS-aware cache way lookup parallel tag comparison data array readout dynamic power OS-aware tuning CMOS static power OS-aware tuning dynamic power static power 9962111 9962306 9962145 / 30 29 6.Conclusions

30. Thanks for your listening 9962111 9962306 9962145 / 30 30