1. Digitally Controlled Oscillators (DCO)
Alicia Klinefelter
ECE 7332
Spring 2011

2. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

3. Why are ADPLLs useful? Problems with analog implementation
Design and verification
Settling time
20 – 30 ms in CPPLLs
10 ms in the ADPLL
Implementation cost
Custom blocks
Loop Filter
High Leakage current
Large capacitor (2) area
Charge Pump
Low output resistance
Mismatch between charging current and discharging current
Phase offset and reference spurs

4. All-digital PLL (ADPLL) TOPOLOGY
DCO
ref(t)
Time-to-Digital
Converter (TDC)
Digital Loop Filter
out(t)
Divider

5. ADPLL: Time-to-digital converter
DCO
ref(t)
Time-to-Digital
Converter (TDC)
Digital Loop Filter
out(t)
div(t)
Divider
Perrott mentions these are a very promising research area!
Delay chain structure sets resolution
Mismatch causes linearity issues
Resolution: want low quantization noise
Architectures
[1, Perrott]

6. ADPLL: DIGITAL LOOP FILTER
DCO
ref(t)
Time-to-Digital
Converter (TDC)
Digital Loop Filter
out(t)
Divider
Compact area
Insensitive to leakage

7. ADPLL: DCO Replaces the VCO from analog implementations
ref(t)
Time-to-Digital
Converter (TDC)
Digital Loop Filter
out(t)
Divider
Replaces the VCO from analog implementations
Consumes 50-70% of overall ADPLL power
Generally consists of a digital controller implementing frequency acquisition algorithm and oscillator.

8. METRICS Power Consumption @ Frequency Phase Noise
Measured with respect to a frequency offset from the carrier
The units, dBm/Hz, define noise power contained in a 1 Hz bandwidth
Jitter
LSB Resolution (ps)
Tuning range
Note: bit resolution is rarely mentioned
Does not seem to have drastic impact on tuning range

9. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

10. EARLY ARCHITECTURES: ANALOG TUNING
Straightforward approach
DAC + VCO
Varactors used initially
Problem with varactors:
Capacitance not very linear with input voltage.
For digital tuning, need flat regions.
Mos varactor formed by depletion cap.
[3, Xu]

11. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

12. OSCILLATORS: Ring oscillator
Frequency determined by delay of the inverters
Each stage provides phase shift where T=2𝑁∆𝑡
Supply voltage
Easy to integrate
High phase noise → Not good for RF applications
Current starved → high resolution, high static power due to current source
Since the total phase during oscillation is 360 degrees, assume each stage creates delta*t phase shift.
𝑛 2 ∉𝑍

13. OSCILLATORS: Lc oscillator
Low phase noise
dissipates only 2𝜋/𝑄 of the total energy stored during one cycle.
Complicated layout
High area
240um
Even for high area of inductor (spiral inductor), Q is moderate at 5-10
[4, Thiel]

14. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

15. NOVELTY: FULLY DIGITAL TUNING
Weighted capacitor networks replaced varactors
Concept of fine and coarse tuning introduced
Coarse (binary weighted) lacks monotonicity
Fine (unit weighted) has monotonicity but complex control
Coarse control used before the PLL locks, fine control used once locking has been established.

16. TECHNIQUE : dithering
To increase resolution, many systems use ΣΔ modulators for dithering the input to the unit caps.
Unit cap determines gain of DCO
Recall, ΣΔ modulators are oversampling converters and produces output pulses proportional to signal changes.
Quantization noise effects
Phase noise goes down as frequency increases
[1, Perrott]

17. NOISE ANALYSIS: DITHERING
[1, Perrott]
Oversampling, Sigma delta, zero-order hold, oscillator
Gain blocks are more or less sinc functions  assume they’re flat at low freqs
If you have an LTI system, the energy spectral density of the output is similar to an eigenvalue of the system.
Since we go from discrete time to continuous time, this relationship can be expressed as: 𝑆 𝑦 (𝑓)= 1 𝑇 𝐻 𝑠 2 𝑆 𝑥 ( 𝑒 𝑗2𝜋𝑓𝑇 )
x[n]
H(s)
y(t)

18. NOISE ANALYSIS: DITHERING
[1, Perrott]
Recall: 𝑆 𝑦 (𝑓)= 1 𝑇 𝐻 𝑠 2 𝑆 𝑥 ( 𝑒 𝑗2𝜋𝑓𝑇 )
𝐻 𝑠 = 1 𝑇 𝐶 𝑇 𝐶 2𝜋 𝐾 𝑣 𝑗2𝜋𝑓 𝐻 𝑛𝑡𝑓 𝑒 𝑗2𝜋𝑓 𝑇 𝑐 𝑆 𝑞𝑟𝑎𝑤 𝑓
= 𝑇 𝐶 𝐾 𝑣 𝑓 1− 𝑒 𝑗2𝜋𝑓 𝑇 𝑐 −

19. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

20. DELAY CELLS: DCM Many traditional delay lines are simple inverters
Chain of tri-state inverters in parallel
Driving capability modulation (DCM)
Changes the driving current of each delay cell by controlling number of enabled tri-state buffers/inverters
Bad power, linearity

21. DELAY CELLS: HYSTERESIS
Hysteresis delay cells (HDC) are relatively new in low power ( ). Trade off power and delay resolution.
Fewer needed to acquire the delay of a many traditional delay cells.
HDCs have wider operating range
Control of driving current to obtain different propagation delay
[2]

22. Implementation Application: Wireless body area networks
Relaxes phase noise requirement
Oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture
Each delay stages is ½ delay of previous
80um x 80um in 90nm CMOS
3.4MHz, 1V supply
Presents two novel HDC topologies
Improves power-to-delay and area-to-delay ratios

23. Implementation: DELAY CELLS
Uses different hysteresis cells for different tuning stages
Need for decoder removed due to power of two delay
Header and footer rarely turned on at same time
Leads to voltage scaling of the cell with hysteresis
[9]
[9]

24. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

25. Architecture: STANDARD CELL
As technology migrates, push towards standard cell implementations for portability.
Goal: implement DCO in HDL
Ring oscillators always used for synthesizeable DCO
Limits implementation options
Most delay cells inverters and NANDs
Controllers simply digital logic

26. PAPER HIGHLIGHTS
Segmented delay line, hysteresis delay cells, and uses standard cells: ultra portable!
140uW MHz) with 1.47-ps resolution
Segmented delay line power gating saves ~25-75% of power
Dependent on operating frequency
[2]

27. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

28. CONTROLLER: LOCKING TIME
New DCO tuning word (OTW) presetting technique to reduce settling time
Three stages in ADPLL
PVT calibration
Frequency Acquisition
Tracking (locked)
Each mode is a search algorithm, each has its own scheme
For ring oscillator, controller implemented in digital logic
For LC oscillator, controller is capacitor bank

29. CONTROLLER: FASTER ALTERNATIVE
Paper [4] designed a new, faster locking algorithm for frequency acquisition.
Locks in 18 clock cycles
Binary search typically used
[4]

30. CONTROLLER: FASTER ALTERNATIVE
PFD produces gain and fast/slow pulse
Mux selects fast/slow gain value
Gain value like the charge pump
As DCO frequency differs more from target, gain increases
Use previous gain with new gain to determine new guess value
[4]

31. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

32. NOVELTY: SUBTHRESHOLD
1.9 GHz DCO in 0.13um technology
2 x 2mm2 using 6 metal layers
Supply voltage at 0.5V, 100uW power
More device transconductance (gm) is available for a given bias current
Application: frequency synthesizer in wireless transceiver
Between calibration, oscillator runs free until next tuning cycle (TX/RX)
Other circuitry turned off
No external components used (even with LC oscillator)

33. OSCILLATOR: LC Based
Differential NMOS only for high output swing for low input voltages
Inductance
Want high Q  determines overall Q of system, startup current, and power consumption
Used bondwire inductances
Want 1fF LSB from caps, but a problem when wiring parasitics on same order of magnitude
[10]

34. CHALLENGE: SMALL CAPACITORS
Capacitor matching a problem for small unit capacitors
Varactors could work
Need flat areas of curve
Testing required to find input voltages of such areas
Switched capacitor implementation using linear capacitors proposed
Routing parasitics reduced
[10]
Change in Cin by ΔC:
∆𝐶= 𝐶 𝑢 𝑁+1

35. Outline Basic Topology of All Digital PLLs (ADPLL) Early Architectures
Where does the DCO fit in?
Early Architectures
Oscillator Background
Current Research
Seminal: All Digital Control [14]
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2]
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10]
A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results

36. DESIGN COMPARISONS: POWER
Op. Freq
Voltage
5.4uW
3.4MGHz
1 V
5.2uw
3.89MHz
8mW
12.3MHz
1.2 V
1.7mW
20MHz
166uW
163.2MHz
140uW
200MHz
110uW
200mhZ
0.8 V
75.9uW
239.2MHz
340uW
450MHz
1.8 V
560MHz
2.3mW
800MHz
0.9 V
23.3mW
1GHz
5.5mW
5.6GHz
0.7 V

37. DESIGN COMPARISONS: FREQ OFFSET

38. DESIGN COMPARISONS: TUNING RANGE

39. RESOURCES CPPSIM Tutorials
[1, Perrot] PLL  Digital Frequency Synthesizers
[2, Perrot] PLL  Voltage Controlled Oscillators
All papers in the bibliography section of Wiki were used for plot generation
Papers [2], [4], [9], [10], [14] addressed in presentation
[3, Xu] Xu, L. (2006, May 18). Digitally controlled oscillator. Retrieved from
[4, Thiel] Thiel, B.T.; Neyer, A.; Heinen, S.; , "Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS," Research in Microelectronics and Electronics, PRIME Ph.D. , vol., no., pp , July 2009.

40. Overview
Move to digital PLL implementations motivated by SoC applications
New digital circuits in ADPLL: TDC, filter, DCO
Ring oscillators versus LC oscillators
Current Research
Initial digital tuning with sigma-delta dithering
Delay cells
Portability
Frequency acquisition algorithm
Sub-threshold operation
QUESTIONS?