1. On the Improvement of Statistical Timing Analysis
Rajesh Garg
Nikhil Jayakumar
Sunil P. Khatri
Department of Electrical & Computer Engineering,
Texas A&M University, College Station.

2. Outline Motivation Previous Work Our Approach Experiments Results
Phase 1
Phase 2
Propagating Arrival Times
Experiments
Results
Conclusions & Future Work

3. Motivation
Increasing process variation has necessitated statistical analysis of timing.
Alternative to performing static timing analysis over several process corners.
Useful way to get better yield estimates.
Current approaches to statistical timing are not readily being accepted by chip designers.
Time consuming
Pessimistic

4. SSTA-Statistical Static Timing Analysis
Based on the principles of Static Timing Analysis (STA).
STA propagates arrival times using SUM, MAX operations.
SSTA: implement SUM and MAX operations for delay distributions.
Identify only structurally long paths.
Such paths may not be sensitizable!

5. SSTA- Sources of Pessimism
Spatial Correlations
Path Correlations
Approximation of PDFs by Gaussian distributions.
Approximation when calculating MAX of two distributions.
False paths.
Assumption that gate delay can be represented by a single Normal distribution.

6. Our Contributions Eliminate False paths
Use a sensitizable timing analysis tool.
Delay for each input transition of a gate is represented by a Normal distribution.
Use the particular Normal distribution corresponding to input transition of a gate that results in large sensitizable delays.
In SSTA, the delay of a gate is represented by a single Normal distribution.

7. Previous Work
“False-path-aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation”, J.-J.Liou et.al (DAC 2002)
First perform traditional SSTA.
Then, attempt to find sensitizable paths.
Assume delay of a gate is represented by a single Gaussian
Ignores difference in input arrival times.
Our Approach:
First find sensitizable input vector transitions, then perform statistical timing analysis.
Allows us to consider the actual input transitions occurring at the inputs of each gate.
Takes input arrival time differences into consideration.

8. Our Approach Phase 1 Phase 2
Find set of sensitizable critical delay transitions. This yields a more accurate analysis
Phase 2
Perform Statistical Timing Analysis on the vector transitions from Phase 1.
Exploit information on input transition at each gate (from Phase 1) to get a yet more accurate analysis.

9. Phase 1: Finding Sensitizable Delay-Critical Vector Transitions
Use the sense package in SIS to find the maximum sensitizable delay.
Sense uses a SAT solver to verify if a particular delay is sensitizable.
Starts with longest structural delay (from static timing analysis).
Keeps reducing delay in fixed steps until a sensitizable maximum delay D is found
Implicitly eliminates false paths.

10. Phase 1: Finding Sensitizable Delay-Critical Vector Transitions
Modified the sense package to return all the primary input vector transitions that cause the largest delays.
Returns primary input vectors that cause these large delays.
Our modification also generates all possible previous values on the primary inputs that cause the output to transition.
Insert complement of largest sensitizable vector in the SAT instance for sense and run sense again iteratively
Repeat until a user-specified number of delay-critical transitions is collected.

11. Phase 2: Compute Output Delay Distributions
Perform Monte-Carlo analysis on set of delay-critical vector transitions.
Propagate arrival times using information on the transition occurring (from Phase 1).
Utilize delay distribution for the actual input transition observed at each gate.

12. Propagating Arrival Times
For regular Static Timing Analysis (for falling output)
Delay = MAX{ (ATa + MAX(D00→11, D01→11)) , (ATb + MAX(D00→11, D10→11)) }
= = 90.3 10 35
90.3 a a
55.3ps c b b
ab → ab
Delay (ps)
00 →11
55.3
01 →11
46.5
10 →11
42.7
55.3ps c

13. Propagating Arrival Times
More accurate estimate for falling output (used in our approach)
Delay = MAX{ (ATa + D00→11), (ATb + D10→11) }
= = 77.7 10 35
77.7
90.3 a a
55.3ps c b b
ab → ab
Delay (ps)
00 →11
55.3
01 →11
46.5
10 →11
42.7
42.7ps c

14. Propagating Arrival Times
For regular Static Timing Analysis (for rising output)
Delay = MAX{ (ATa + MAX(D11→00, D11→01)) , (ATb + MAX(D11→00, D11→10)) }
= = 88.0 10 35
88.0
50.5ps a a c b
53.0ps b
ab → ab
Delay (ps)
11→00
30.5
11→01
50.5
11→10
53.0 c

15. Propagating Arrival Times
More accurate estimate for rising output (used in our approach)
Delay = MIN{ (ATa + D11→01), (ATb + D11→00) }
= = 60.5 10 35
60.5
88.0
50.5ps a a c b
30.5ps b
ab → ab
Delay (ps)
11→00
30.5
11→01
50.5
11→10
53.0 c

16. Propagating Arrival Times
NAND2: 00→11
NAND2: 11→00
Plot of output delay with different input arrival times.
STA and our new approach are compared with SPICE
One input transitioning at a fixed time.
Swept transition time of other input

17. Propagating Arrival Times
Similarly for a 3-input NAND3 gate with inputs {a,b,c} and output {O}.
For falling output transition – all inputs need to switch to logic 1.
000→100→110→111
ATout = MAX{ (ATa + D000 →111), (ATb + D100 →111), (ATc + D110 →111) }
For rising output transition – only one of the inputs needs to switch to logic 0.
111→011→001→000
ATout = MIN{ (ATa + D111 →011), (ATb + D111 →001), (ATc + D111 →000) }

18. Experiments Standard-cell library of 8 cells
INV1X, INV2X, NAND2, NAND3, NAND4, NOR2, NOR3, NOR4.
Used SPICE to characterize the cells.
Used 0.1um BPTM process.
Parameter
Nominal Value σ L
0.1 u
0.005 u
VTn V
0.013 V
VTp V V
Variations applied
Created table of values for mean and standard deviation of the delay for all possible transitions for a set of loads.

19. Delay Distribution example
Delay of a gate cannot be represented by a single Gaussian distribution.
Depends on input transitions.
NAND2: Rising output transition
NAND2: Falling output transition

20. Experiments Phase 1 Phase 2
Compute top 50 delay-critical vector transitions.
Phase 2
Use knowledge of input transitions at each gate from Phase 1.
Propagate arrival times (using method discussed).
Propagate 1000 times
For each transition, choose a random value of delay from a Gaussian distribution.
Use values of m and s from a pre-characterized table for the particular vector transition appearing at the gate.
Use same m + ns delay point for all input transitions of gate

21. Experiments
Compared our approach (StatSense) with Monte-Carlo based SSTA (10000 MC iterations).
Compared results for a set of ISCAS and MCNC benchmark circuits.
Also compared results from 50 critical vector transitions versus 25 critical vector transitions.
1000 MC runs for each vector transition.

22. StatSense with 50 vectors
Results
Ckt
SSTA
StatSense with 50 vectors
μ (ps)
σ (ps)
μ+3σ (ps)
runtime (s)
μ+3σ
Ratio
runtime(s)
runtime
ratio
alu2
19.08
278.8
661.25
17.69
714.32
0.67
1991.5
7.14
alu4
18.21
1289.4
560.2
753.01
23.74
824.23
0.64
3386.8
6.04
apex6
680.51
10.95
713.36
632.2
447.66
26.36
526.74
0.74
895
1.41
apex7
489.79
8.16
514.27
207.5
427.17
12.89
465.84
0.9
260.6
1.25
C499
737
11.29
770.87
419.4
617.92
14.55
661.57
0.86
481.6
1.15
C1355
714.82
8.59
740.59
484.8
418.08
11.47
452.49
0.61
578.1
1.2
cordic
669.99
8.6
695.79
657
578.18
18.5
633.68
0.91
657.23 1 i6
496.16
22.8
564.56
353
449.55
19.84
508.52
609.5
1.73 i7
496.25
21.76
561.53
514.3
449.31
20.6
511.11
494.9
0.96
rot
781.23
13.75
822.48
571
501.65
17.24
552.72
1343.6
2.35 x1
319.34
10.4
350.54
261.5
269.43
13.7
310.1
0.88
277.14
1.06
AVG
0.79
2.29
Our approach (StatSense) is significantly less pessimistic.
Takes ~2.3X more time to run (50000 MC runs compared to 10000)

23. StatSense with 50 vectors StatSense with 25 vectors
Results
Ckt
SSTA
StatSense with 50 vectors
StatSense with 25 vectors
μ+3σ (ps)
runtime (s)
μ+3σ
Ratio
runtime
ratio
alu2
278.8
0.67
7.14
0.68
4.42
alu4
1289.4
560.2
0.64
6.04
0.63
5.74
apex6
713.36
632.2
0.74
1.41
0.77
0.716
apex7
514.27
207.5
0.9
1.25
0.91
0.62
C499
770.87
419.4
0.86
1.15
0.57
C1355
740.59
484.8
0.61
1.2
0.6
cordic
695.79
657 1
0.54 i6
564.56
353
1.73
0.83 i7
561.53
514.3
0.96
0.65
rot
822.48
571
2.35
1.42 x1
350.54
261.5
0.88
1.06
AVG
0.79
2.29
0.8
1.51
StatSense with 25 vector transitions takes only 50% more time than SSTA.
Runtime is not 5X (for 50 vector transitions) or 2.5X (for 25 transitions)
If there is no transition at output of a gate, delay computations in the fanout of a gate can be avoided.
No such pruning possible in SSTA.

24. Example – apex7 Delay histogram is significantly less pessimistic.
Circuit delay is not a Gaussian distribution.

25. Conclusions and Future Work
Current statistical timing analysis approaches are pessimistic.
Pessimism due to false paths and
Assumption that delay of a gate can be represented by a single Gaussian distribution.
Our approach is significantly less pessimistic.
Future work
Decrease runtimes.
Explore methods to find the minimum number of vector transitions required to get a realistic statistical timing result.

26. THANK YOU!

27. Phase 1: Finding Sensitizable Delay-Critical Vector Transitions
Use the sense package in SIS to find the maximum sensitizable delay.
Sense uses a SAT solver to verify if a particular delay is sensitizeable.
Starts with longest structural delay (from a static timing analysis).
Keeps reducing delay in steps till a delay D is sensitizable.
Implicitly eliminates false paths.
Modified sense package to return all the primary input vector transitions that causes this maximum delay.
Returns current primary input vector that causes this maximum delay.
Also, generate all possible previous values of the primary input vector that cause the output to transition.
Insert complement of largest sensitizable vector in sense’s SAT instance and run sense again.
Repeat till a large-enough (user-specified) set of delay-critical transitions is collected.

28. Propagating Arrival Times
Naïve estimate
Delay = MAX(ATa, ATb) + D00→ = = 90.3 10 35
90.3 a a
55.3ps c b b
ab → ab
Delay (ps)
00 →11
55.3
01 →11
46.5
10 →11
42.7
55.3ps c

29. Results
test