1. ECE 331 – Digital System Design
Decoders and Encoders
(Lecture #14)

2. ECE 331 - Digital System Design
Decoders
ECE Digital System Design

3. Decoders
A decoder selects 1 of 2N output lines by decoding a binary value on the N input lines.
(similar to a 1-to-2N Demultiplexer)
ECE Digital System Design

4. Decoders: Definitions
Active – the function is being performed
Active low – active when the output is 0.
Active high – active when the output is 1.
Enabled – active circuit can perform its function
Low-level enabled
circuit performs its function when its Enable = 0.
High-level enabled
circuit performs its function when its Enable = 1.
ECE Digital System Design

5. ECE 331 - Digital System Design
Decoder: N-to-2N w n 1 – N
inputs En
Enable 2
outputs y
Active-high or active-low
ECE Digital System Design

6. ECE 331 - Digital System Design
Decoder: 2-to-4 1 y w
(c) Logic circuit x En 2 3
(a) Truth table
(b) Graphical symbol
enabled
disabled
ECE Digital System Design

7. ECE 331 - Digital System Design
Decoder: VHDL
Implement the boolean expressions using a functional model for the architecture
Alternately, VHDL provides powerful constructs that make it easier
Concatenate operator (&)
Concatenates 2 or more signals or vectors to create a larger vector
New_Vector <= Vector1 & Signal1;
With-Select-When construct
Analogous to a Switch (or Case) statement
ECE Digital System Design

8. ECE 331 - Digital System Design
Decoder: 2-to-4 (VHDL)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS ;
END Behavior ;
Concatenate
With-Select-When
ECE Digital System Design

9. ECE 331 - Digital System Design
Decoder: 3-to-8 w 2 y 1 3 En 4 5 6 7
2-to-4 Decoder
ECE Digital System Design

10. Decoder: 4-to-16 En w y Second decoder stages use 2 LSB's8 9 10 11 w 2 1 3 En 4 5 6 7 12 13 14 15
First decoder stage uses 2 MSB's
Second decoder stages use 2 LSB's

11. Designing Logic Circuits using Decoders
ECE Digital System Design

12. Decoders: Designing Logic Circuits
Each row in a Truth Table corresponds to a minterm
Each minterm can be mapped to a decoder output
For each row in the Truth Table, where the output of the function is one (F = 1),
Sum (“OR”) the corresponding outputs of the decoder to realize the logic function
ECE Digital System Design

13. Decoders: Designing Logic Circuits
Exercise:
Design a circuit, using a 2-to-4 Decoder to realize the Boolean expression given below.
FX,Y = Sm(0,2)
ECE Digital System Design

14. Decoders: Designing Logic Circuits
F = Sm(0,2)
ECE Digital System Design

15. Decoders: Designing Logic Circuits
Exercise:
Design a circuit, using a 3-to-8 Decoder to realize the Boolean expression given below.
FX,Y,Z = Sm(1,4,5,7,8)
ECE Digital System Design

16. Decoders: Designing Logic Circuits
Exercise:
Design a circuit, using 2-to-4 Decoders to realize the Boolean expression given below.
FX,Y,Z = Sm(1,4,5,7,8)
ECE Digital System Design

17. ECE 331 - Digital System Design
Encoders
ECE Digital System Design

18. An encoder outputs the binary value of the active input.
ECE Digital System Design

19. ECE 331 - Digital System Design
Encoder
Inverse operation of the decoder
Decoder selects one output based on the input binary number.
Encoder outputs the binary number based on the selected input.
Issues
What if more than one input is active?
What if no inputs are active?
ECE Digital System Design

20. ECE 331 - Digital System Design
Encoder: 2N-to-N w y N 2 N
inputs
outputs y n – 1 w 2 n – 1
The active (or selected) input is encoded on the n outputs.
ECE Digital System Design

21. ECE 331 - Digital System Design
Encoder: 4-to-2 1 w 3 y 2 w 1 y 2 3
ECE Digital System Design

22. ECE 331 - Digital System Design
Encoder: 8-to-3
ECE Digital System Design

23. ECE 331 - Digital System Design
Priority Encoder
Higher-order input has priority of lower-order input
Order of the input determined by its binary value
I0 has binary value 000 (0)
I1 has binary value 001 (1)
I2 has binary value 010 (2)
I3 has binary value 011 (3)
etc.
So,
I1 selected over I0
I2 selected over I1 and I0
I3 selected over I2, I1, and I0
ECE Digital System Design

24. ECE 331 - Digital System Design
Priority Encoder
Valid indicator
Output signal of the (priority) encoder that indicates the validity of the encoded output
Encoded output is invalid when no inputs are selected or when the encoder is disabled
V = 0 (indicates invalid encoded output; active high)
Encoded output is valid when one, or more, input(s) is (are) selected, and encoder is enabled
V = 1 (indicates valid encoded output; active high)
ECE Digital System Design

25. Priority Encoder: 4-to-21 w y z x 2 3
Valid indicator
invalid
valid
ECE Digital System Design

26. Priority Encoder: 4-to-2 (VHDL)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ARCHITECTURE Behavior OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END Behavior ;
4 input bits
valid indicator
2 output bits
Active-high
inputs and outputs
ECE Digital System Design

27. Priority Encoder: 4-to-2 (VHDL)
ARCHITECTURE Behavior OF priority IS
BEGIN
WITH w SELECT
y <= "00" WHEN "0001",
"01" WHEN "0010",
"01" WHEN "0011",
"10" WHEN "0100",
"10" WHEN "0101",
"10" WHEN "0110",
"10" WHEN "0111",
"11" WHEN OTHERS ;
z <= '0' WHEN "0000",
'1' WHEN OTHERS ;
END Behavior ;
ECE Digital System Design