1. Request-Response Trace for Bus Performance Analysis
Dr. Neal Stollon
Jan. 2007

2. Introduction
MIPS Technologies is Leader in High Performance Embedded RISC Processors
MIPS32® 34KTM Multi-threaded RISC Processor
SoC-IT Platforms
Best in class applications and tools eco-systems
FS2 is Instrumentation IP and Tools Division of MIPS
On-Chip Instrumentation (OCI®) Leadership
Integrated Trace and Analysis Solutions for Embedded Processor, Logic and On- Chip Bus IP
Leading edge on-chip analysis tools for MIPS based systems – RRT performance analysis as only one example

3. SoC Analysis and Debug Issues
Visibility and optimization is crucial to embedded design success
Difficult to fix/optimize what you can not see -
Unexpected on-chip Inter-relationships not always intuitive
System on Silicon Instrumentation Requirements
Visibility - into non-observable sub-system interfaces
On-chip analysis complements EDA verification
Interoperable control with processor debug capabilities
Cross-triggering, synchronization for full view of problems
Reasonable gate size and trace speeds
Range of features configurable to system requirements
IO requirements
Leverage existing debug interfaces i.e. JTAG
High performance IO allows more extensive trace

4. SoC On-Chip Instrumentation Evolution
JTAG
(Scan, BIST
Run Ctrl)
Embedded
Processor /
Logic Trace
Analysis
Tools
ICE /
BDM
System Level Embedded Instrumentation
MIPS Solutions
EJTAG
PDtrace
Navigator RRT
Platform SoC (Multi-Core)
50K
20K 8K
2.5K 1K
SoC
(RISC+IP
+RAM)
Debug-
Difficulty
(gates/pins)
ASICS
Embedded Systems
1980s
1990s
2000s
The New Frontier
Complexity of Embedded Analysis requirement keeps increasing
Gates increase geometrically - Pins increase linearly
Significant bandwidth for leading architectures
More complex analysis needs Instrumentation

5. Modeling and Verification Abstraction
Pre-silicon –
EDA based analysis
Post-silicon –
In System centric analysis
System
Platform
Focus on Hardware Bugs
Focus on Software Bugs
Application
Software
RTOS
Integration
System
Analysis
Focus
Core IP
System
Initialization
Multi-core
Integration issues
RTL
Diagnostics
Instruction Level/
Bus Functional
Point were Hardware is
“assumed working”
ESL
Hardware
Simulation
Hardware
Prototype/Emulation
Software Debugger
System platform
Modeling and Verification Abstraction

6. Drivers for Request Response Trace
Analysis of complex on chip interconnection networks
Need to analyze transfer/response latencies
Lower overhead analysis for critical information
OCP
socket
OCP
socket
AHB
socket
AXI
socket
bridge
bridge
bridge
Initiator Agent IA IA IA RP RP RP PP RP RP PP RP
Shared Link
fabric
dedicated
XBar
fabric
links RP PP RP RP PP RP
Target
Agent TA TA
bridge
bridge
OCP
AHB
OCP
socket
socket
socket
Source: Sonics, Inc.
Other
Layers TA
APB
socket

7. RRT as a Performance Analysis Trace System
Multicore
Processor trace
Analyzer tools
processor trace
Mictor 1
System
Trace
Probe
MIPS
OCP IF
RRT agent –
OCP capture, filter, format
JTAG port
Synch
signals
USB
Ethernet
HOST PC
(Win/Linux)
RRT OCP
agent -
Other core
OCP IF
Combiner/
Scheduler
“trace funnel”
Navigator RRT Trace
Port
Selected
IP IF
RRT custom agent - b
Mictor 2
RRT AHB
agent -
DMA
AHB IF
Trace funnel provides prioritized transfers
Agents provide in line filtering formatting of bus data

8. Point-to-point Timing
System Performance Measurements
Point-to-point Timing
A to B event timing measurements: event A starts counter, event B stops counter
read out duration via JTAG port, or
save counter values into trace then zero counter in single cycle
Benefit: measure loop times of algorithms, task executions, interrupt handlers, waiting for resource
Trace Performance Profiling
Trace history of counted values
Observe change in measured values over multiple occurrences
Example: multiple durations between A-B events
Benefit: see how loop times change over the real-time execution on system

9. System Level Performance Analysis
Types of analysis that are important
Measure activity - bus utilization, caches efficiency, co- processors, interrupts, peripheral device events
Measure latencies - interrupts, bus access, DMA transfers
loop times of processing network packets, DSP Blocks
Monitoring bus bandwidth utilization, efficiency
Caches hit/miss ratios, DRAM pages, processor stalls
RRT provides Analysis of System operations
Timestamping for interval measurements relative to real time
Counter and trigger resources for real time event rates or duration measures

10. On Chip Performance Trace - RRT
Cross Triggers
PDtrace
EJTAG
MIPS
core
Other IP blocks
(video, imaging )
Trace
Funnel RR
Trace
Agents
JTAG &
TRACE
PORT
(To SNP
IO)
JTAG
TAP RR
Trace
Agents
System Bus
Fabric RR
Trace
Agents
Other IP
Selective trace capability
Simple event monitoring
Triggers, counters in probe
Probe based Trace filtering and alignment
Trace limited by Port Bandwidth

11. Instrumented RTL files
RRT Debug Flow
Customer
EDA tools Environment
RRT IP Integration
Instrumentation
configuration file
design
RTL files
SYNTHESIS
Place & Route
To target
Instrumented RTL files
Trigger/ Trace
Requirements
Analyzer
configuration
VCD Export
Trace data
(from SNP)
Trace and post processing GUI

12. Mobileye EyeQ2 Analysis Needs
Complex automotive image processing IC
10 cores (MIPS 34K, DSPs, DMA)
Complex OCP/AMBA system network
Multi-layer Sonics SMX
Complex memory subsystems
Debug Performance and bottlenecks
Analyze bus latencies and throughput
Trace bus control transactions of concurrent transactions (34K, DSP, DMA)
Trace full address for any transaction
Correlate Bus transactions to PDtrace
Track active threads to bus operations
Trace at least one image frame (>1 Gbyte)
Low overhead debug solution (minimal buffering)
Reduced operating speed OK
Pins available for dual trace ports

13. RRT Instrumentation for Mobileye
Request-Response Trace – Real time Bus Transaction Analysis
Solution built around SNP
64 pin target interface
Allows processor and bus trace
Deep (2 Gbyte) Probe Trace Buffer
Multi-frame trace
Complex triggers, timestamps, . . .
RRT agents and funnel IP
Minimized on chip Logic
Complex trace resources in probe
Upgraded PDtrace™ for multicore trace
Multicore PDtrace Funnel IP
PDtrace/RRT Correlation in SW
Request-Response delay analysis
PDtrace/RRT Bus Correlation
Mictor 1
Mictor 2
JTAG port
FS2
System Probe
RRT Agent
(capture,
filter,
format)
RRT
Trace
Port
RRT Trace Funnel
(combiner/
Scheduler)
MIPS 0
(34K 2x OCP)
MIPS 1
DMA
(AHB)
VCE
(XB1
OCP)
Multicore
PDtrace
Funnel/

14. First Silicon Solutions Introduces System Navigator Pro™ Series of High Performance Trace Probes
Next-Generation Hardware Platform Addresses SoC Debug and System-Level Verification
PORTLAND, OR, Jan. 30, First Silicon Solutions (FS2), a division of MIPS Technologies, Inc. (NASDAQ: MIPS), today announced the production release of System Navigator Pro™, a high performance high capacity trace probe family designed to address complex SoC debug and system-level verification

15. New System Navigator Pro Probe
System Navigator Pro (SNP) provides next generation probe technology for debug applications that require massive amounts of off-chip trace capture
Supports all JTAG functions of Sys Nav probe
38-pin Mictor target IO (up to 2 per probe)
32 bits of trace data per Mictor connection
Up to 2G byte deep trace buffer
Supports trace bandwidth of up to 16 Gbps
Target interface speed up to 500MHz
USB 2.0 and 10/100/1G Ethernet PC interfaces
Supports current MDI 3rd party tools interface
SNP provides value added analysis with
Malta boards
FPGA based prototyping environments
Systems Emulation tools
System Level Debug Initiative Support
Capture of large amounts of bus and processor data for post processing

16. System Debugger Environment Architecture
FS2 In System Analyzer (ISA) - Standards based IDE
Plug and play with all MDI complaint 3rd party tools
User transparent concurrent debug access (many cores/many debuggers)
Eclipse, Tcl/TK, MDI, XML, text based scripting and configuration
Common
Tcl/Tk CLI
BusTrace and Triggering GUI
GDB SDK
Optional
Eclipse IDE
3rd Party Source
Level Debuggers
MDI
Windows MABILib/MDILib DLL
PC Interface
FS2 System Navigator JTAG Probe
Off-Chip
Trace Port
JTAG Port
Trace Funnel
On-Chip
MIPS
Processor
Core
Trace RAM
Bus Trace OCI
PDtrace OCI
EJTAG
Cross
Trigger
Bus Data

17. System Navigator Pro RRT support
Provide correlated view of processor and bus operations
latency measurements outside of core visibility
Common views of core and system performance
Migration to unified display and GUI

18. Trigger Trace from Applications or IP
Processor operations can drive analysis operations
ex. Cross-Triggering Bus Trace with MIPS Source Code
Trigger bus trace from Breakpoint
Use bus condition as breakpoint input

19. FS2 = Comprehensive Debug Solutions
On-Chip Instrumentation IP
MIPS Processor Instruments
Integrated Bus Analyzers
Multi-Core debug
Performance Analysis
Application specific/custom debug blocks
System Navigator Probes
USB 2.0, Ethernet and ECP host PC
connections
14-pin (EJTAG & on-chip PDTrace)
or 38-pin Mictor (EJTAG & off-chip
PDTrace) target connections
Integrated with MIPS SDE software
Low speed and RTCK support for
emulation systems integration
Software Tools and Interfaces
Integrated w/MIPS GDB
Complete EJTAG & PDTrace support
On-chip and off-chips trace tools
Performance Monitoring tools
Supports 3rd party debugger and
RTOS interfaces