Presentation is loading. Please wait.

Presentation is loading. Please wait.

EE201C Chapter 3 Interconnect RLC Modeling

Published byMabel Wells Modified over 5 years ago

Similar presentations

Presentation on theme: "EE201C Chapter 3 Interconnect RLC Modeling"— Presentation transcript:

1 EE201C Chapter 3 Interconnect RLC Modeling
Prof. Lei He

2 Chapter 3 Interconnect RLC Modeling
Table and formula based capacitance extraction Table and formula based inductance extraction RC or RLC circuit model generation

3 Reading Assignments J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, June 1997, pp L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", (nomination for Best Paper Award)IEEE Custom Integrated Circuits Conference, San Diego, CA, pp , May 1999. M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp , March 2001.

4 Capacitance Extraction
Introduction Table lookup method Formula-based method

5 What’s Capacitance? Simplest model: parallel-plate capacitor +Q -Q
++ ++ Simplest model: parallel-plate capacitor It has two parallel plates and homogeneous dielectric between them The capacitance is  permittivity of dielectric A area of plate d distance between plates The capacitance is the capacity to store charge charge at each plate is one is positive, the other is negative

6 General Picture c12 m2 m1 c23 c13 m3
For multiple conductors of any shapes and materials, and in any dielectric, there is a capacitance between any two conductors Mutual capacitance between m1 and m2 is C12 = q1/v2 q1 is the charge of m1 v1 =0 and v3 = 0

7 Capacitance Matrix m1 m3 m2 c23 c13 c12 C = -c21 c22 -c23 -c31 -c32
Capacitance is often written as a symmetric matrix m1 m3 m2 c23 c13 c12 C = -c21 c22 -c23 -c31 -c32 c33 c11 -c12 -c13 is the self-capacitance for a conductor e.g., c11 =c12+c13 The charge is given by e.g.,

8 Application in VLSI Circuits
Conductors: metal wire, via, polysilicon, substrate Dielectrics: SiO2 ,... Total cap for a wire delay, power Mutual cap between wires signal integrity

9 Characteristics of Coupling Capacitance
Coupling capacitance virtually exists only between adjacent wires or crossing wires Cx Capacitance can be pre-computed for a set of (localized) interconnect structures

10 2.5D Capacitance Extraction [Cong-He-Kahng-et al, DAC’97]
Propose and validate five foundations to simplify capacitance extraction Develop a simple yet accurate 2.5D capacitance extraction

11 Verification of Foundations
Method: 3D analysis by FastCap [Nabors-White, TCAD’91] Geometrical parameters: process [NTRS’94] 3.0 2.5 1.0

12 Key Factor to Enable Foundations
Minimum metal density requirement Metals occupy > 30% area on anywhere on routing layer Foundry may introduce dummy metals for metal sparse areas dummy metal

13 Foundation I Effect of Ground and Neighbors
Both ground, and neighboring wires on the same layer, have significant shielding effects. Thus, both must be considered for accurate modeling.

14 Shielding Effect of Ground and Neighbors
layer i Ci,i Ci,i-2 no GND 458.4 130.1(28.4%) layer i-2 Ci,i lumped capacitance for victim on layer i Ci,i-2 coupling between victim and aggressor on layer i-2

15 Shielding Effect of Ground and Neighbors
layer i Ci,i Ci,i-2 no GND 458.4 130.1(28.4%) + GND 486.6 79.49(16.3%) layer i-2 Ci,i lumped capacitance for victim on layer i Ci,i-2 coupling between victim and aggressor on layer i-2

16 Shielding Effect of Ground and Neighbors
layer i Ci,i Ci,i-2 no GND 458.4 130.1(28.4%) + GND 486.6 79.49(16.3%) + neighbors 1428 24.77(1.8%) layer i-2 Ci,i lumped capacitance for victim on layer i Ci,i-2 coupling between victim and aggressor on layer i-2

17 Foundation II Coupling between Layers i and i-2
Coupling between wires on layer i and wires on layers i-2 is negligible when the metal density on layer i exceeds a certain threshold.

18 Coupling between Layers i and i-2
layer i layer i-1 layer i-2 -- 2x 4x 8x 12x Ci,i Ci,i-2 Ci,i lumped capacitance for victim on layer i Ci,i-2 coupling between victim and aggressor on layer i-2

19 Foundation III Coupling Effect of Layers i+2 and i-2
During capacitance extraction for wires on layer i, layers i+2 and i-2 can be treated as ground planes with negligible error. There is no need to look beyond layers i+2 and i-2.

20 Coupling Effect of Layers i+2 and i-2
Ci,i 418.9 Ci,i+1 52.35 Ci,i-1 52.26 Ci,i lumped capacitance for victim on layer i Ci,i+1 coupling between victim and central crossover on layer i+1 Ci,i-1 coupling between victim and central crossunder on layer i-1

21 Coupling Effect of Layers i+2 and i-2
Ci,i Ci,i+1 Ci,i-1 Ci,i lumped capacitance for victim on layer i Ci,i+1 coupling between victim and central crossover on layer i+1 Ci,i-1 coupling between victim and central crossunder on layer i-1

22 Foundation IV Coupling Effect of Neighbors
Coupling analysis to wires on the same layer need only consider nearest neighbors independently, with the widths of same-layer neighbor wires having negligible effect on the coupling.

23 Effect of Non-immediate Neighbors
victim layer i Cl Cr Ci,i 1436 C l 616.6 Cr 616.5 Ci,i: lumped capacitance for victim.

24 Effect of Non-immediate Neighbors
victim victim layer i Cl Cr Cl Cr Ci,i (0%) C l (+3%) Cr (+3%) Ci,i: lumped capacitance for victim.

25 Effect of Neighbor Widths
layer i victim w W Ci,i Ci,i varies less that 0.3% for different neighbor widths.

26 Independence of Neighbors
2 victim (S1,S2) (1,2) (1,3) (1,4) (1,) lhs rhs Ci,i differs less than 1.0%.

27 Foundation V Interaction between Layers i-1 and i+1
The joint interaction of layers i-1 and i+1 on layer i is negligible; therefore, corrections for orthogonal crossovers and crossunders can be performed independently.

28 Independence of Crossovers and Crossunders
layer i+2 i+1 i i-1 couplings between victim and crossunders No crossover

29 Independence of Crossovers and Crossunders
layer i+2 i+1 i i-1 couplings between victim and crossunders No crossover Full of crossovers

30 Independence of Crossovers and Crossunders
layer i+2 i+1 i i-1 couplings between victim and crossunders No crossover Full of crossovers

31 Table-Based 2.5D Capacitance Extraction
Table (Cap coefficients) generation One-time use of 3-D method Capacitance computation table lookup with linear interpolation and extrapolation

32 Table Generation for Lateral, Area and Fringe Capacitances
layer i w s s Functions of (w,s) Pre-computed for per-side per unit-length

33 Table Generation for Crossing Capacitances
w s sc wc layer i Function of (w,s,wc,sc)

34 Table Generation for Crossing Capacitances
sc wc wc sc sc w w Ci,i Per-corner Cover(w,s,wc,sc) = 4

35 Illustration of Capacitance Computation
victim Compute the lumped cap for victim

36 Find Nearest Neighbors on Same Layer
victim

37 Add in Per-Side Area, Fringe and Lateral Capacitances
victim w S1 L1 Per-side area capacitance = CA(w,s1) * L1 Per-side fringe capacitance = CF(w,s1) * L1 Per-side lateral capacitance = CL(w,s1) * L1

38 Add in Per-Side Area, Fringe and Lateral Capacitances
victim

39 Find All Crossovers and Crossunders
victim

40 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc sc w One-corner crossover correction = Cover(w,S1,wc,sc)

41 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc w One-corner crossover correction = Cover(w,S1,wc,)

42 Add in Crossing Capacitances Corner-by-Corner
victim S1 wc w One-corner crossover correction = Cover(w,,wc,)

43 Add in Crossing Capacitances Corner-by-Corner
victim wc sc w One-corner crossover correction = Cover(w,,wc,sc)

44 Summary of Capacitance Computation
Find nearest neighbors on the same layer Add in per-side lateral, area and fringe capacitances w.r.t. each neighbor Find all crossovers and crossunders Add in crossing capacitances corner-by-corner w.r.t. each crossover and crossunder Sum of capacitance components in above steps is the lumped capacitance of the victim.

45 Good match in terms of lumped capacitance!
Experimental Results 2 1/2-D 3-D Error net1 pF 6.5713pF -0.54% net2 pF pF -3.33% Good match in terms of lumped capacitance!

46 Formula based on horizontal and vertical parameters
[Sakurai-Tamaru,ED’83][Wu-Wong-et al, ISCAS’96] single line parallel lines …...

47 Single Line [Sakurai-Tamaru,ED’83]
w t Ff Ff h Fp Unit-length cap Error less than 6% when

48 Single Line of Length L [Sakurai-Tamaru,ED’83]
w t h Line of length L

49 Parallel Lines on Same Layer [Sakurai-Tamaru,ED’83]
w s w t h Unit-length cap Error less than 10% when

50 Parallel Lines on Same Layer [Wu-Wong-et al, ISCAS96]
h Unit-length cap Recall [Sakurai-Tamaru,ED’83]

51 Noramlzied space (s/h)
Comparison 6 numerical Wu-Wong-et al 5 Sakurai Normalized cap (C/) W=1.05um 4 W=0.7um 3 1 2 3 4 15 Noramlzied space (s/h) [Wu-Wong-et al] is better in smaller width and spacing

52 Parallel Lines within Two Grounds [Wu-Wong-et al, ISCAS96]
Two grounds where One ground

Download ppt "EE201C Chapter 3 Interconnect RLC Modeling"

Similar presentations

EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.

EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.
EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.
UCLA Modeling and Optimization for VLSI Layout Professor Lei He

UCLA Modeling and Optimization for VLSI Layout Professor Lei He
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.

Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.
EE466: VLSI Design Lecture 11: Wires

EE466: VLSI Design Lecture 11: Wires
EE 447 VLSI Design Lecture 5: Wires. EE 447VLSI Design 6: Wires2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering.

EE 447 VLSI Design Lecture 5: Wires. EE 447VLSI Design 6: Wires2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering.
Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.

Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.
Weiping Shi Department of Computer Science University of North Texas HiCap: A Fast Hierarchical Algorithm for 3D Capacitance Extraction.

Weiping Shi Department of Computer Science University of North Texas HiCap: A Fast Hierarchical Algorithm for 3D Capacitance Extraction.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,
Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,

Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,
Lecture #25a OUTLINE Interconnect modeling

Lecture #25a OUTLINE Interconnect modeling
Introduction to CMOS VLSI Design Interconnect: wire.

Introduction to CMOS VLSI Design Interconnect: wire.
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.
Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.

Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.
Lecture 24: Interconnect parasitics

Lecture 24: Interconnect parasitics
UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.

UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.
Circuit Characterization Feb 4, 2005. Basic Device Equations (p.51)  Cutoff region: V gs  V t  I ds = 0  Linear/non-saturation region: 0

Circuit Characterization Feb 4, Basic Device Equations (p.51)  Cutoff region: V gs  V t  I ds = 0  Linear/non-saturation region: 0
THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.

THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.

Similar presentations

Ads by Google