1. ME 4447/6405 Microprocessor Control of Manufacturing Systems and
Introduction to Mechatronics
Instructor: Professor Charles Ume
Lecture #6

2. Review Digital Arithmetic

3. Hexadecimal – Base 16 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 1517 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30

4. Octal – Base 8 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30

5. Conversion from base 10  base 16  base 2 and back  base 10
Example 1: 67410 32 10
Remainder 2
Remainder A 64 34 2 -
Read -
Read Remainders backwards
Therefore, = 2A216 =

6. Example 1 Cont’d 2A216 to base 10: = 2 x 160 + A x 161 + 2 x 162
= 67410
to base 10:
= 0 x x x x 23
+ 0 x x x x 27
+ 0 x x x x 211

7. Conversion from base 10 to 2
This method known as “repeated division by 2.”
Example 2: Convert 3710 to base 2.
Remainder 1
Remainder 0
Read
Stop dividing when the answer is 0. The remainders are read in reverse order
to form the answer.
Therefore, 3710 = = (Note: 2 front bits added for 8-bit processor)

8. Example 3 Convert 110.1112 to the decimal system Solution:
= (1 x 2-3) + (1 x 2-2) + (1 x 2-1)
+ (0 x 20) + (1 x 21) + (1 x 22) = =

9. Example 4 Convert 2A2.516 to the decimal system Solution:
2A2.5 = (5 x 16-1) + (2 x 160) + (A x 161)
+ (2 x 162) = =

10. Example 5 Convert 0.7510 to Binary Solution: 0.75 x 2 = 1.50  1
Therefore, = 0.112
Read

11. Example 6 Convert 0.301710 to Binary Solution: 0.3017 x 2 = 0.6034  0
Therefore, = ……
Read

12. Two’s Complement Arithmetic
The circuitry required for computers to add binary numbers is relatively simple. However, since circuitry to subtract binary numbers is very difficult to design and build, another subtraction method would be desirable. The method is subtraction by addition of the 1’s or 2’s complements of the number. Subtraction by the addition of 1’s complement requires much more hardware to implement.
Most computers on the market perform subtraction by the addition of 2’s complement. Therefore we will concentrate only on subtraction by 2’s complement.
How to obtain 1’s and 2’s complements:
Binary number =
1’s complement =
2’s complement =
When subtraction is performed the answer can be positive or negative, depending upon the relative values of the minuend and subtrahend (e.g. a-b). We must, therefore, in some way account for the sign of the answer.

13. The most significant bit (MSB) is used as the sign bit
The most significant bit (MSB) is used as the sign bit. If the MSB is a ‘1’, the number represented by the remaining 7 bits is assumed to be negative and is represented by its 2’s complement. If the MSB is a ‘0’, the number represented in the remaining seven bits is positive and is equal to the binary equivalent of these seven bits.
Example 1: 1710 – 610=(1116 – 616)
= 616
= 1’s complement of 616
= 2’s complement of 616
= 1116
= 616 in 2’s complement
= + 0B16 =

14. Example 2: 610 – 1710 = (616 – 1116)
= 1116
= 1’s complement of 1116
= 2’s complement of 1116
= 616
= 1116 in 2’s complement
= - ( ) = = - 0B16 or
Note: C and N bits will be set. C is set to 1 because the absolute value of subtracthend (17) Is larger than the absolute value of the minuend (6)

15. Since bit 7 serves as the sign bit
Since bit 7 serves as the sign bit. A ‘0’ in bit 7 indicates a positive number. Thus the maximum positive number an 8-bit processor can represent in 2’s complement is or 7F16 or
Likewise a ‘1’ in bit 7 indicates a negative number. The minimum negative number that an 8-bit processor can represent in 2’s complement is 8016 ( ).
Its 2’s complement is – ( ) = - ( ) = =
It is possible to (add) or subtract two numbers and get invalid answer, especially when the answer is out of the range of –128  +127
This situation is referred to as 2’s complement overflow. If a subtraction (or addition) is performed and 2’s complement overflow occurs the V bit will be set to a ‘1’ otherwise it will be cleared.

16. Example 3: =
8510 = 5516 =
= 1’s comp. of 5516
= 2’s comp. of 5516
9010 = 5A16 =
= 1’s comp. of 5A16
= 2’s comp. of 5A16
= (2’s comp. of 5516)
= (2’s comp. of 5A16)
= = +8110
V bit will be set.
C bit will be set.

17. Example 4: 4D
positive
positive
negative
V bit is set.

18. S X H I N Z V C MC9S12C CONDITION CODE REGISTER MASKING BITS
S – Disables STOP instruction when set.
X – Masks XIRQ Request when set.
set by hardware reset, cleared by software
set by unmasked XIRQ
See page 116 of Technical Data
I – Masks interrupt request from all IRQ level
sources (both external and internal) when
set.
set by unmasked I level request or unmasked XIRQ
ARITHMETIC BITS
Reflect results of instruction execution
C – Carry/Borrow from MSB unsigned
arithmetic
V – 2’s complement overflow indication
signed arithmetic
Z – Zero result
N – Negative (follows MSB of result)
H – Half Carry from bit 3 to bit 4
ADD operations only
H will be set to 1

19. Logic Gates

20. Logic Gates Why do we study Logic Gates?
Used to Determine Status or Occurrence of Events

21. “AND” Function
Symbol
Equation
Input A
Output C 1 B
C = A ● B

22. “OR” Function
Symbol
Equation
Input A
Output C 1 B
C = A + B

23. C = A + B “Exclusive OR” Function (XOR) Symbol Equation Input A Output1 B
C = A + B

24. “Not” Function (Inverter)
Symbol
Equation
Input A
Output C 1
C = A

25. “NOR” Function
“NAND” Function
Input A
Output C 1 B
Input A
Output C 1 B

26. QUESTIONS???