1. Lecture 1: Introduction
UCSD ECE 111
Prof. Farinaz Koushanfar
Fall 2017
Some slides are courtesy of Prof. Lin

2. Course info Instructor: TA and helpers: Office Hours
Prof. Farinaz Koushanfar
Jacobs Hall #6401
TA and helpers:
Main TA: Keith Yu ( all questions to main TA)
Bita Darvish Rouhani
Siam Umar Hussain
Office Hours
Instructor: Tues 12-1:50pm, Jacobs (EBU1) #6401
By appointment

3. ECE 111, fall 2017 Lectures: Tues/Thurs 2-3:20PM
Location: MANDE, Room B150
Discussion session: Wed 2-2:50PM
Location: Center Hall, Room #212

4. ECE 111 Course goals
Digital Circuit design using the hardware description (SystemVerilog) Language
Use tools to simulate and implement circuits in the SystemVerilog
Using commercial CAD tools for Field Programmable Logic Arrays (FPGAs)
Implementing designs and optimizing
Complex digital designs from algorithms to implementation
Hands-on projects
The name “SystemVerilog” describes hardware at the same level as “Verilog”, but it adds a number of enhancements and improved syntax
SystemVerilog files have a “.sv” extension so that the compiler knows that the file is in SystemVerilog rather than Verilog.

5. More info on ECE 111 Various types of activities
Lectures
Design tools
Discussion sections – design examples
The central resource for this course:
Course website
TritonEd
Announcements, slides, syllabus, homework, project assignments and submission
Piazza
Discussion board

6. Course text Recommended textbook
Digital Design and Computer Architecture, Second Edition, by David Harris and Sarah Harris
We will only be using Chapter 4 of this book, which provides a good overview of SystemVerilog with good examples.
Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog
Book recommended, but not required.
This is NOT a lecture-based class. Class time used to talk about SystemVerilog in the beginning, but mostly about specific examples and project information for the rest of the quarter.

7. Software Design tool: Vivado HLx Webpack edition
Xilinx ISE (Integrated Synthesis Environment) is a tool for synthesis("compilation") and analysis of HDL designs on Xilinx FPGAs
Simulation tool: ModelSim PE Student Edition
Links to software download and basic tutorials on the class website

8. Course work 6 project assignments Final project
You need to do the smaller project assignments to be able to do the final project
Final project will be evaluated on 2 criteria:
Best delay = number of clock cycles x clock period
Best area/delay = area x delay
Last three projects, including the final one, done in teams of 2 students.

9. Honor code The UCSD student conduct code
conduct/regulations/22.00.html
Violations will be reported to the Student Conduct Office
Accommodations available for students with disabilities, religious and ethnic holidays, and illness (with proper documentation)

10. Syllabus (detailed schedule on the website)
Week 1: Introduction, intro to SystemVerilog and ModelSim environments
Week 2: Combinational and sequential logic in SystemVerilog (P1)
Week 3: FPGA and number conversion in System Verilog (P2)
Week 4: Finite state machines in System Verilog (P3)
Week 5: Testbenches and parameterizable modules in SystemVerilog (P4)
Week 6: Handshaking and FPGA implementation issues
Week 7: Design area and performance optimization (P5)
Week 8: Finite Impulse Response (FIR) filter and its variants (Final Porject)
Week 9: Final project discussions and testbenches
Week 10: Summary and final project optimization (Project due 12/10/17)

11. Lectures Lectures are based on slides – both great and bad
Slides are great
Organizes the course material
Great addition to the textbook
Can use pictures and animation to explain
Slides are bad
Well-known that instructors teach faster by slides
They make hard things look easier than they are
They can make you fall asleep
I encourage you to be proactive and take notes
I may use the board when/if necessary

12. Back to digital design basics

13. Basic digital circuit design components

14. Sequential circuits
Circuit whose output values depend on current and previous input values
Include some form of storage of values
Nearly all digital systems are sequential
Mixture of gates and storage components
Combinational parts transform inputs and stored values

15. Flip flops and clocks Edge-triggered D-flipflop Timing diagram
stores one bit of information at a time
Timing diagram
Graph of signal values versus time

16. How to represent hardware?
If you’re going to design a computer, you need to write down the design so that:
You can read it again later
Someone else can read and understand it
It can be simulated and verified
Even software people may read it!
It can be synthesized into specific gates
It can be built and shipped and make money
UCSD ECE 111, Prof. Koushanfar, Fall'16

17. Ways to represent hardware
Draw schematics
Hand-drawn
Machine-drawn
Write a netlist
Z52BH I1234 (N123, N234, N4567);
Write primitive Boolean equations
AAA = abc DEF + ABC def
Use a Hardware Description Language (HDL)
assign overflow = c31 ^ c32;
Slide courtesy of Prof. Milo Martin, Upenn

18. Hardware description language (HDL): allows
designer to specify logic function only. Then a
computer-aided design (CAD) tool produces or
synthesizes the optimized gates.
Most commercial designs built using HDLs
Two leading HDLs:
– Verilog
developed in 1984 by Gateway Design Automation
became an IEEE standard (1364) in 1995
– VHDL
Developed in 1981 by the Department of Defense
Became an IEEE standard (1076) in 1987

19. HDLs Textual representation of a digital logic design
Can represent gates, like a netlist, or abstract logic
HDLs are not “programming languages”
No, really. Even if they look like it, they are not.
For many people, a difficult conceptual leap
Similar development chain
Compiler: source code  assembly code  binary machine code
Synthesis tool: HDL source  gate-level specification  hardware

20. Pros and cons Why using an HDL? Easy to write and edit Compact
Don’t have to follow a maze of lines
Easy to analyze with various tools
Why not to use an HDL?
You still need to visualize the flow of logic
A schematic can be a work of art
But often isn’t!

21. Synthesis vs. Simulation
Extremely important to understand that SystemVerilog is BOTH a “Synthesis” language and a “Simulation” language
Small subset of the language is “synthesizable”, meaning that it can be translated to logic gates and flip-flops
SystemVerilog also includes many features for “simulation” or “verification”, features that have no meaning in hardware!
Although SystemVerilog syntactically looks like “C”, it is a Hardware Description Language (HDL), NOT a software programming language
Every line of synthesizable SystemVerilog MUST have a direct translation into hardware (logic gates and flip flops)
Very important to think of the hardware each line of SystemVerilog produce

22. SystemVerilog
Hello World!

23. Simple logic gate in SystemVerilog
Module
module not_gate(in, out); // module name+ports
// comments: declaring port type
input in;
output out;
// Defining circuit functionality
assign out = ~in;
endmodule

24. System Verilog

25. Synthesis SystemVerilog:
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Synthesis: translates into a netlist (i.e., a list of gates and flip-flops, and their wiring connections)
* Schematic after some logic optimization

26. Basics of digital design with HDL
Stimulus block
Circuit Under Design (CUD)
Generating inputs to CUD
Checking outputs of CUD 4 8
Test bench

27. Useless SystemVerilog Example
module useless;
initial
$display(“Hello World!”);
endmodule
Note the message-display statement
Compare to printf() in C

28. SystemVerilog Syntax Case sensitive No names that start with numbers
Example: reset and Reset are not the same signal.
No names that start with numbers
Example: 2mux is an invalid name
Whitespace ignored
Comments:
// single line comment
/* multiline
comment */

29. Hierarchical modeling concepts
SystemVerilog HDL
Hierarchical modeling concepts

30. Design methodologies

31. Hierarchical design

32. A simple design methodology

33. Hierarchical design
Circuits are too complex for us to design all the detail at once
Design subsystems for simple functions
Compose subsystems to form the system
Treating subcircuits as “black box” components
Verify independently, then verify the composition
Top-down/bottom-up design

34. Synthesis
We usually design using register-transfer-level (RTL) Verilog
Higher level of abstraction than gates
Synthesis tool translates to a circuit of gates that performs the same function
Specify to the tool
the target implementation fabric
constraints on timing, area, etc.
Post-synthesis verification
synthesized circuit meets constraints

35. Physical implementation
Implementation fabrics
Application-specific ICs (ASICs)
Field-programmable gate arrays (FPGAs)
Floor-planning: arranging the subsystems
Placement: arranging the gates within subsystems
Routing: joining the gates with wires
Physical verification
Physical circuit still meets constraints
Use better estimates of delays

36. What we have learned today…
Digital systems use discrete (binary) representations such as gates and FFs
Combinational and sequential circuits
History of Verilog HDL
Principals of digital design using HDL
Our first design example…