1. 241-440 Computer System Design Lecture 6
Wannarat Suntiamorntut

2. Part I: Data Path (Multicycle)

3. What’s wrong when CPI=1

4. Memory access time
Physics
Use hierarchy of memories

5. Reduce the cycle time
Cut combinational dependency graph and insert register or latch

6. Partial the CPI = 1

7. Multi cycle datapath

8. Flow with R-type instruction

9. Flow with I-type instruction

10. Flow with Load instruction

11. Flow with Store Instruction

12. Flow with Branch Instruction

13. Minimizes Adder/ memory

14. The control Model State specify control point for register transfer
Transfer occurs upon exiting state

15. Control Specification for multicycle

16. Traditional FSM controller

17. Map RT to Control Points

18. Assign State

19. Detail in Control Specification

20. Controller Design Instructions have short sub-sequence.
Use microsequencer
microprogramming

21. Jump counter

22. Using Jump Counter

23. Microsequencer

24. Microprogram Control

25. Summary Disadvantage of single cycle long cycle time
cycle time is too long for all instructions except the load
Multiple Cycle
Divide instructions into small steps
Execute each step in one cycle

26. Next on Lecture 7