1. 32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING
PRARDIVA MANGILIPALLY ELEC 6270

2. OUTLINE: Objective Basic idea Basic gating circuit
Modified clock gating circuit
Design platform
Results
Conclusion

3. OBJECTIVE:
To measure the average power for a 32 bit parallel load register with and without clock gating.
To compare the results for the same.
To study the effect of clock gating on power consumption for a 32 bit parallel load register.

4. CLOCK GATING:
Clock gating is one of the power saving techniques in which additional logic is added to a circuit to prune the clock tree ,thus disabling portions of circuitry so that flipflops do not change state.As a result switching power goes to zero.

5. MODIFIED CLOCK GATING CIRCUIT:

6. Design platform: Latchfree clock gating circuit
Tools used: Modelsim, leonardo, Design Architect, Eldo
Technology: tsmc018
Clock frequency: 50MHz
Operating voltage: 1.8V

7. Pattern:0000000 Without clock gating Average power: = 242.6818U W
With clock gating
Average power: U W

8. Pattern:111111111 Without clock gating With clock gating
Average power: UW
With clock gating
Average power: UW

9. Pattern:101010 Without clockgating Average power:457.2622uW
With clock gating
Average power: U W

10. PATTERN:10111011 WITH CLOCK GATING AVERAGE POWER:337.1065UW
WITHOUT CLOCKGATING:
AVERAGE POWER: UW
WITH CLOCK GATING
AVERAGE POWER: UW

11. PATTERN:01000100 WITH CLOCKGATING AVERAGE POWER:331.2031UW
WITHOUT CLOCKGATING
AVERAGE POWER: UW
WITH CLOCKGATING
AVERAGE POWER: UW

12. PATTERN:11011101 WITHOUT CLOCKGATING: AVERAGE POWER:352.7703UW
WITH CLOCKGATING:
AVERAGE POWER: UW

13. PATTERN:00100010 WITHOUT CLOCKGATING AVERAGE POWER:344.7696UW
WITH CLOCKGATING
AVERAGE POWER: UW

14. INPUT12:
WITHOUT CLOCK GATING:
AVERAGE POWER: UW
WITH CLOCK GATING:
AVERAGE POWER: UW

15. INPUT12:
WITHOUT CLOCKGATING:
AVERAGE POWER: UW
WITH CLOCKGATING:
AVERAGE POWER: UW

16. Power Reductions: Without clock gating With clock gating
TRANSITION DENSITY
EXPECTED POWER
(UW)
OBSERVED POWER
POWER REDUCTION
(%)
0.0000
88.77
0.0004
82.35
0.1000
49.21
0.1024
42.73
0.2500
5.51
0.5000
-37.5

19. CONCLUSIONS:
Clock gating technique effectively reduces dynamic power in most of the cases.
However,it increases power when there are transitions in every clock cycle.This increase is due to the extra power consumed by the ex-nor and nor gates in the clock gating circuit which account to about 58% increase in total hardware.
If this increase in hardware could be reduced then the power savings can be increased even in the worst case which calls for the implementation of a different clock gating circuit or the usage of low power ex-or’s discussed in the class.

20. REFERENCES:
Class lecture slides at COURSE/ E6270_Spr09/course.html
Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG2000(This paper discusses a method to avoid premature truncation of the clock).

21. THANK YOU