1. Daniel Klopp, Yao Yao, Hoa Nguyen, Roy Rabindranath December 1, 2009
2/19/ :50 AM
D.R.Y.H. LOW POWER SRAM
Daniel Klopp, Yao Yao, Hoa Nguyen,
Roy Rabindranath
December 1, 2009
© 2008 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries.
The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

2. Presentation Outline Why Us? Overview of Design Block/Array Components
Results
Metric Table
Special Features
Issues
Conclusion

3. Why Choose Our Design? Meets Specification!
2/19/ :50 AM
Why Choose Our Design?
Meets Specification!
Optimal Balance of Power, Speed, Leakage, Cell Area and Robustness
Environmentally Friendly
Low Cost
The Future is in Low Power!
© 2008 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries.
The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

4. Design Overview 1Mb Metric: (Total Power)2 * delay * area = 4822
2/19/ :50 AM
Design Overview
1Mb
Metric: (Total Power)2 * delay * area = 4822
32 Blocks
256 Rows per Block
4 Words per Row
32768 Bits per Block
© 2008 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries.
The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

5. Array Diagram

6. Block Diagram

7. Bit Cell CR=1.7 > 1.2 PR=1.0 < 1.8
Bit Cell=137.7um2 (140.16um2 eff.)
Block= 4.59 mm2
Bit Cell

8. 8 Bit Row Decoder
Uses NOR-NAND Static Style

9. Write Driver

10. Sense Amp

11. Clock / Results

12. Clock / Results

13. Metric Table Metric Value Bitcell Area 137.7um2 (140.16um2 eff.)
2/19/ :50 AM
Metric Table
Metric
Value
Bitcell Area
137.7um2 (140.16um2 eff.)
Total Area
~ 150mm2
Total Power
732 uW
Read Delay
60 ns
Write Delay
Total Delay
Project Metric
(0.732) 2 * 150 * 60 = 4822
© 2008 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries.
The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

14. Special Features Pulse Clocking Banking Mechanism
Very Low Voltage Operation (1.5V)

15. Issues Peripheral Layouts Incomplete
LVS checks difficult with larger components
Can take multiple hours per block
Simulating actual circuit not possible
A 256x128 block simulation crashed Cadence
Noise Margin at low voltages decreased
Still operational
Less noise tolerance

16. Conclusion
Questions?