1. Physics of Semi- conductor Devices
Chapter 3. MOSTransistor Structre and Operation
3.2.1 Punchthrough
3.2.2 MOSFET Capacitances
3.2.3 Small-signal Behavior
3.2.4 Device Speed
3.3 MOSFET Scaling
Institute of Microelectronics
GUO Dapeng

2. 3.2.1 Punchthrough
Considering a MOSFET to which a small Vgs(<Vth)is applied and Vds=0.so that the devices is off. An energy barrier exists between the source and the the region under the gate, it is this barrier that holds the electrons in the source.The only current that flows is the drain leakage current of the reversed biased drain -substrate junction. The space-charge depletion width at the source and drain ends are symmetrical .

4. Applying a positive Vgs(>Vth) lower the energy barrier, thus allowing electrons to move from the source and form a conducting channel connecting the source and the drain.
Now if Vds is increase with Vgs held constant,then the depletion width of the drain becomes closer to the source.
If Vds is increased still further,eventually at a certain drain voltage the drain depletion width touches the source.

5. When this happens a large amount of current flows even though the gate has been biased to turn the device off. The gate loses control over the drain and the device fails to operate normally. this phenonmena is called punchthrough and Vds induced current is called the punchhrough current.The coresponding drain voltageVds that causes a small but finite amount of drain current at or near zoro Vgs is called punchthrough voltage Vpt.

6. In short-channel devices, punchthough causes breakdown of the source/drain junctions. The effect of the punchthrough on the MOSFET current-voltage character is show in fig.2
fig.2

7. 3.2.2 MOSFET Capacitances
The I-Vcharacteristcs in front chapter are steady-state or DC characteristcs of a typical MOSFET. The transient behavior of a MOSFET is due to the device capacitive effects, which in fact are the results of the charges stored in the device.
The stored charges are(1) the inversion charge Qi in the inversion or channel region, (2) the bulk charge Qb in the depletion region underlying the channel, (3)the gate charge Qg(=Qi+Qb), (4) the charges due to the source/drain pn junctions.

8. These charges give rise to the device capacitances shown in Fig3
These charges give rise to the device capacitances shown in Fig3. From the point of developing MOSFET dynamic or transient models, it is instructive to divide the device into two parts:
Fig 3

9. 1.The intrinsic part which forms the channel region of the devices (dashed line in Fig 3).The charges which are responsible for the transistor action are the gate charge Qg, the depletion or bulk charge Qb and the inversion charge Qi. The capacitances arising from these charges are called intrinsic capacitance. Thus, the capacitances Cgs,Cgd and Cgb are the intrinsic capacitances. The simple first order MOSFET capacitance model assumes only these three intinsic capacitance,but in fact there are many more as we shall see in Chap7.these intrinsic capacitances are normally derived from the charges which are used to

10. to calculate the steady-state current Ids
to calculate the steady-state current Ids. Thus, the capacitance expressions do not involve any new parameters other than those required for Ids calculations (chapt 7)
2 The extrinsic part which includes the source and drain pn junction portion of the MOSFET. Note that in the extrinsic part there is an inevitable overlap of the gate over the source and drain region. The capacitance arising from this overlap are called gate overlap capacitances show as Cgso and Cgdo in Fig 3

11. The source and drain pn junction capacitances (Cbs and Cbd) plus the gate overlap capacitances are called extrinsic capacitances. These extrinsic capacitances are often called parasitic capacitances of the MOSFET.
The capacitive characteristics of a MOSFET are then the sum of the intrinsic and extrinsic capacitances. It is these capacitances which are responsible for limiting overall device performance in terms of device switching speed.

12. 3.2.3 Small-Signal Behavior
Under normal operation, a voltage applied to the gate, drain or substrate results in a change in the drain current. The ratio of change (increase) in the drain current to the change (increase) in the gate voltage while keeping drain and substra voltages (Vds and Vbs) constant is called gate transconductance or transconductance gm ,
gm=đIds/đVgs|Vds,Vbs
The transconductance gm is one of the important device parameters as it is a measure of device gain.

13. gm=u Cox(W/L)Vds (linear region)
gm=u Cox(W/L)(Vgs-Vth) (saturation region)
where u is mobility of the carriers in the channel region, Cox is the gate oxide capacitance per unit area, W/L is device width to length ratio,and Vth is threshold voltage.
Thus, the gain of MOSFET can be increased by
Increase Cox, that is,use MOSFET with a thinner gate oxide
Use devices with higher carrier mobility u. u elec>u hole, so, g elec > g hole ,gnmos>gpmos

14. Use devices with larger cahnnel width W and short channel length L,while decreasing L,scaling consideration must be taken into account as discussed in section 3.3
It should be pointed out that though Eq(3.9a) shows that gm in the linear region is cnstant independent of the gate voltage voltage Vgs, in real devices gm varies with Vgs,being maximum at low Vgs. This discrepancy is due to the assumption f constant u (indepdent of Vgs),while in reality u is Vgs and Vds dependent as we shall see later in section 6.6.

15. For the same reason, in real devices gm in saturation is Vds dependent while Eq(3.9b) predicts constant gm. see Fig 4
In addition to gm,the MOSFET has two other conductances. The ratio of change in the drain current due to change in Vbs for a fixed Vgs,and Vds is called substrate transconductance gmbs.
gmbs=đIds/đVbs|Vgs,Vds
and the radio of change in the drain current to the change in the drain voltage is called drain conductance or simply conductance gds
gds=đIds/đVds|Vgs,Vbs

16. Fig 4 shows plot of gm,gmbs and gds as a function of Vds and Vds
Vgs=2V
Vds=2V

17. If all the voltages are changed simultaneously,then the corresponding total change in the drain current is
đIds=gm*đVgs+gd*đVds+gmbs*đVbs
If the change in the voltages is small, approaching zero, then these transconductances are small transconductances

18. 3.2.4 Device Speed
The ratio of transconductance gm to the gate input capacitance CG,gives a relative measure of the swithching speed of the device.
CG is simply that of a parallel plate capacitance of area WL and thickness tox,CG=WLCox
gm/CG=u(Vgs-Vth)/L*L,where we made use of Eq gm=u Cox(W/L)(Vgs-Vth).

19. Note the Eq depents only up on the length of the channel and not on the width. Thus, increasing the channel width increases the gate capacitance as much as the transconductance and no increase in the speed is achieved.
Thus, to increase device speed, the channel length L should be as short as possible.
However, due to the device extrinsic capacitances(S/D junction and gate overlap capacitances) , the switching speeds of the actual devices are much less than that predicted by the above equation.

20. 3.3 MOSFET Scaling
MOS transistor have been systematically scaled down in dimensions in order to achieve increased circuit density and higher performance. Rulers of scaling were first proposed by Dennard et al. with the idea of reducing the device dimensions while still mantaining the current-voltage behavior of a large device.
According to this rule,all horizontal and vertical device dimensions as well as voltage are scaled down by a factor K>1,called the scaling factor while the doping concentration Nb is increased by the same factor.

21. MOSFET
Scaling rules
generalized scaling
constant voltage
scaling
constant
field scalling
quasi-constant voltage scaling
parameters
W,L,X /K /K /K /K
tox /K /v /K /K
Nb K K K K*K/v
Vdd /K /V /v

22. This scaling rule,often known as classical or constant feild scaling, results in electric fields inside the device that are unchanged compared to the unscaled or original device.
The effect of keeping the electric field unchanged in the scaled device is to avoid undesirable high feild efffects such as mobility degradation, impact ionization, hot-carrier effect etc.

23. It is worth pointing out that not all device parameters scale proportionally. For example, subthreshold slope does not scale.This means that subthreshold current in scaled devices becomes larger while current above threshold is reduced.
This is undesirable for digital circuit design because it means that it will be difficult to turn off the device.
In addtion to this, for practical and standardization reasons the supply voltage was not scaled as per the scaling rules.

24. In order to minimize the undesirable high electric field in the devies, due to unscaled votage, the gate oxide was scaled by a factor v which is less than K (K>v>1)
Nonetheless, in this case of the so called constant voltage scaling,the electric fields can still be very large, resulting in undesirable effects.
This has lead to alternative schemes of scaling in which supply voltage does not scale as fast as the device dimensions.

25. The quasi-constant voltage scaling is the same as cinstant voltage caling except that the voltage is scaled by a factor v. this means that the electric field will be smaller compared to constant voltage scalling.
In the generalized scaling law, scaled devices perform some where between constant field and constant voltage scaling.

26. MOSFET
Scaling rules
generalized scaling
constant voltage
scaling
constant
field scalling
quasi-constant voltage scaling
parameters
W,L,X /K /K /K /K
tox /K /v /K /K
Nb K K K K*K/v
Vdd /K /V /v

27. 示例