1. Image compression on reconfigurable FPGA for the SO/PHI space instrument
D. Hernández Expósito, J.P. Cobos Carrascosa, J.L. Ramos Mas, M. Rodríguez Valido, D. Orozco Suárez, J.C. del Toro Iniesta
SpacE FPGA Users Workshop, 4th Edition
9-11 April 2018
European Space Research and Technology Centre (ESTEC) 1

2. Table of contents
Solar Orbiter / Polarimetric Helioseismic Imager (SO/PHI)
Introduction
Compression requirements
Digital Processing Unit
FPGA Image Compression Core for SO/PHI
CCSDS-IDC Introduction
Discrete Wavelet Transform (DWT)
Bit plane Encoder (BPE)
Results and conclusions

3. SO/PHI: Introduction
Solar Orbiter / Polarimetric Helioseismic imager (SO/PHI)
Perihelium: 0.28 AU
SO/PHI: magnetograph
Insufficient telemetry
20Kb/s downlink!

4. SO/PHI: Compression requirements
24 raw images
(2K x 2K pixels)
5 science images
On board data pipeline: compression factor 33.4 !
Detector
Pre-processing
RTE Inversion
Compression
To Ground
3Gbit
3Gbit
320Mbit
92Mbit
Compression requirements:
Losless/lossy compression
Images of different sizes (up to 2K x 2K pixels)
Dynamic range 16 bpp

5. SO/PHI: Digital Processing Unit
Xilinx FPGA#1
(Virtex-4 SX55)
Compression
Fiethe, B.; Bubenhagen, et al., "Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument," NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2012

6. Table of contents
Solar Orbiter / Polarimetric Helioseismic Imager (SO/PHI)
Introduction
Compression requirements
Digital Processing Unit
FPGA Image Compression Core for SO/PHI
CCSDS-IDC Introduction
Discrete Wavelet Transform (DWT)
Bit plane Encoder (BPE)
Results and conclusions

7. FPGA Image Compression Core for SO/PHI
Consultative Committee for Space Data Systems – Image Data Compression (CCSDS-IDC 122,0-B-1)
Compression mode:
Lossless and lossy
Grayscale images up to 16 bits per pixel (revision B-1)
Aimed to spacecraft applications
Good trade-off compression performance vs complexity
Hardware implementation
Input image
Discrete
Wavelet
Transform
(DWT)
Bit Plane Encoder
(BPE)
Compressed Data

8. FPGA Image Compression Core for SO/PHI
Architecture overview
SoCWire DPU network

9. FPGA Image Compression Core for SO/PHI
3-level 2-Dimensional Discrete Wavelet Transform
1D - 9/7 DWT :
9/7 Integer DWT
Only integer operations
Complexity ↓
Lossless and lossy
9/7 Float DWT
Float operations
Complexity ↑
lossy
Compression effectiveness at low bit rates ↑
2D-DWT
DC's coefficients
2D-DWT
2D-DWT
AC's coefficients
Level 1
Level 2
Level 3
3-Level 2D-DWT

10. FPGA Image Compression Core for SO/PHI
DWT Simple Intruction Multiple Data (SIMD) – Mutltiprocessor Net
Parameterized ALU:
32 bits Float Point
+, *, CCSDS-round, Float point to integer conversión
24 bits Fixed Point ALU
+, *, CCSDS-round
Integer/Float DWT compliant
Smart Buffer net:
Inspired in CCSDS memory efficient DWT calculation.
Row to column transposition
BRAM line buffers
Same processor used in the RTE Inversor  reduce the time for development

11. FPGA Image Compression Core for SO/PHI
Bit Plane Encoding process
Segment: group of S consecutive blocks
Block: spacial region of the image (1 DC + 63 AC’s)
Segment Dynamic Range parameters: BitDepthDC, BitDepthAC and BitDepthAC_block_m
Segment size (S blocks per segment) implications:
S ↓  protection against errors ↑
S ↑  Compression effectiveness ↑
S ↑  Memory resources ↑
BitdepthAC_block_m
Segment Header
DC's coefficients
[DPCM + RICE]
Initial coding of DC coeffcients
Coded AC bit depths
Coded bit plane BitDepthAC-1
Coded bit plane BitDepthAC-2
[Bitplane + VLC]
Coded bit plane b
AC's coefficients
DWT image
partitioned into segments
First segment coding
Coded bit plane 0

12. CCSDS-IDC: FPGA implementation
Bit Plane Encoder architecture
Calculates every dynamic range parameters online:
BPE starts whenever a segment is generated.
The same block to DC’s and BitdepthAC_m encoding:
Minimum resource usage
AC CODER
It holds two segments:
A segment is encoded meanwhile the next one is being generated.
Up to 256 block/segment.
Fabric BRAMs in Dual-Port RAM configuration.

13. Table of contents
Solar Orbiter / Polarimetric Helioseismic Imager (SO/PHI)
Introduction
Compression requirements
Digital Processing Unit
FPGA Image Compression Core for SO/PHI
CCSDS-IDC Introduction
Discrete Wavelet Transform (DWT)
Bit plane Encoder (BPE)
Results and conclusions

14. Results Architecture configurability VHDL parameters
User configurable parameters
Allowed values
Discrete Wavelet Transform
9/7 Integer DWT, 9/7 Float DWT
CustomWtFlag
0, 1
CustomWt
0, 1, 2, 3
ImageWidth (pixels)
[128:64:2048]
ImageHeight (pixels)
[64:64:2048]
S (blocks/segment)
32 >= S <= 256, power of 2
SegmByteLimit (bytes)
[0 - 2^17]
BitplaneStop
[0 – 32]
StageStop
VHDL parameters
Soft-Register configurable

15. Results FPGA Image Compression Core for SO/PHI – Flight Model
XC4VSX55 FPGA implementation statistics:
Image size: up to 2048x2048
Dynamic range: 16 bits/pixel
9/7 Integer DWT (lossless and lossy)
Segment size: up to S = 256 blocks
Occupied Slices
12,000 (50%)
Occupied BRAM
168 (60%)
Occupied DSP48E
62 (12%)
Maximun Frecuency
150 MHz
Maximum Throughput
30 MHz
2 seconds/image

16. Conclusions System On Chip solution Not external memory
Very low resource occupancy
Virtex-4 SX55
High S (blocks per segment) values
Versatility:
Integer & Float DWT
Different image sizes
Lossless/lossy
Good performance
>30 times faster than software implementations (LEON3)
First CCSDS-IDC Coder on a reconfigurable FPGA for an ESA mission (SO/PHI FM)

17. << dhdez@iaa.es >>
Image compression on reconfigurable FPGA for the SO/PHI space instrument
D. Hernández Expósito, J.P. Cobos Carrascosa, J.L. Ramos Mas, M. Rodríguez Valido, D. Orozco Suárez, J.C. del Toro Iniesta
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