1. NA Silicon Wafer Committee Liaison Report
SEMICON Japan
December 5, 2008

2. Meeting Information Last meeting Next meeting
Wednesday, Nov 12, 2008, NA Fall Meetings, San Jose, CA
Next meeting
Meeting site has been decided and finalized.
Tuesday, March 31, 2009, NA Spring Meetings, Vancouver, Canada
1:00 – 5:00 PM
NA Silicon Wafer Committee Liaison Report

3. NA Silicon Wafer Committee
Committee Chairmen
Dinesh Gupta /STA
Noel Poduje /SMS
NA Silicon Wafer Committee Liaison Report

4. Silicon Wafer Committee Specifications Metrology Committee
C: Dinesh Gupta - STA
C: Noel Poduje - SMS
TE: Murray Bullis - Materials & Metrology
Specifications
Metrology
Committee
Int’l Annealed Wafers TF
Dinesh Gupta -STA
Int’l Advanced Wafer Geometry TF
Paul Langer - Komatsu Silicon
Int’l Test Methods TF
Dinesh Gupta - STA
Int’l Epitaxial Wafers TF
Dinesh Gupta - STA
Paul Langer - Komatsu Silicon
Int’l Advanced Surface Inspection TF
John Stover - The Scatter Works
George Kren - KLA Tencor
Int’l Terminology TF
Murray Bullis - Materials & Metrology
Int’l SOI Wafers TF
George Celler - SOITEC
CMP Process Metrics TF
Polysilicon TF
Int’l Polished Wafers TF
Murray Bullis - Materials & Metrology
Int’l 450 mm Wafer TF
Mike Goldstein - Intel
Int’l Specification Order Form TF
Reclaim Wafers TF
Premium Wafers TF
Liaison with Japan
Test Wafers TF
MEMS Wafers TF
NA Silicon Wafer Committee Liaison Report

5. NEW SNARFs New SNARFs approved:
Revision to SEMI MF , Test Method for Thickness and Thickness Variation of Silicon Wafers
add 9-point pattern
NA Silicon Wafer Committee Liaison Report

6. Ballots Ballots reviewed from San Jose, CA, meeting
None
All ballots were adjudicated at Stuttgart, Germany
Except for Doc 4211 Rev. of M62(epi wafer) – to be reviewed at SEMICON Japan
Ballots for Spring 2009, Vancouver Canada.
Revision to SEMI MF , Test Method for Thickness and Thickness Variation of Silicon Wafers
NA Silicon Wafer Committee Liaison Report

7. Metrology Group
Int’l Advanced Wafer Geometry TF/Paul Langer (Komatsu Silicon) & Noel Poduje (SMS)
Converting preliminary to full standards:
Preliminary stds have two year life (e.g SEMI M , Moving Average) will be removed from web and CD on March 2010)
M (ESFQR), M (ZDD), M (Partial Site) – all done
M (Roll-Off Amount, ROA) – failed, will be reballoted
Publication extension permission is being submitted to ISC
Discussing doc. 3335B Test Method for Measuring and Reporting Nanotopography of Unpatterned Silicon Wafers for 130 nm to 65 nm
Considering an Edge Profile STEP at West ‘09
NA Silicon Wafer Committee Liaison Report

8. Metrology Group Edge Profile WG (Win Baylies/BayTech group)
Drafting documents:
Doc. 4428A [Guide for Specifying Edge Profile (EP7)]
Failed and return to WG for further rework and reballot
Doc is expected to be submitted in January 2009
Doc [Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles (EP6)]
Approved and published as SEMI M
NA Silicon Wafer Committee Liaison Report

9. Metrology Group
Int’l Advanced Surface Inspection TF/John Stover (The Scatter Works) & George Kren (KLA-Tencor)
Balloted doc.4583B, Rev. to M , Practice For Calibrating SSIS Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces
To allow reference particle materials other than polystyrene latex (PSL) spheres
Ballot failed in Stuttgart
Reballoted; informal discussion of negative in SJ
Discussed revision for M Guide for Specifying SSIS for Silicon Wafers for the 130 nm, 90 nm, 65 nm, and 45 nm Technology Generations, to extend to 22 nm
NA Silicon Wafer Committee Liaison Report

10. Specifications Group Int’l 450 mm Wafer TF/Mike Goldstein (Intel)
Doc. 4442, New Standard: Specification for 450mm Diameter Mechanical Handling Polished Wafers
Approved at SEMICON West and published as SEMI M
Drafting doc. 4624, New Standard: Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers
Doc has been circulated among TF members and will be reviewed at SEMICON Japan.
Doc is expected to ballot at SEMICON West ‘09
NA Silicon Wafer Committee Liaison Report

11. Specifications Group Int’l SOI Wafer TF/George Celler (SOITEC)
M (SOI Wafer) will be expanded by:
Consolidating parts of M47 into M71 (M47 would be withdrawn after the expanded M71 is approved)
Adding some parameters of strained SOI (sSOI)
Adding metrology procedures for sSOI and updating some SOI metrology
Correcting some definitions
Revision proposal is approved as SNARF 4497
Doc. is expected to be balloted for cycle 1 of 2009
NA Silicon Wafer Committee Liaison Report

12. Specifications Group
Int’l Epitaxial Wafer TF/Paul Langer (Komatsu) & Dinesh Gupta (STA)
Balloted doc. 4211, Revision to SEMI M Specifications for Silicon Epitaxial Wafers
To include 32 nm Technology Node for Epi Wafers; Flatness, LPDs, NT, Surface Metals, Bulk Metals, Thickness Uniformity, Concentration Uniformity, Edge Exclusion, and ERO
Results to be discussed at SEMICON Japan
Next project is working on 22 nm epi guide, TF will survey industry for guidance.
NA Silicon Wafer Committee Liaison Report

13. Specifications Group
Int’l Polished Wafer TF/Murray Bullis (Materials & Metrology)
Balloted doc. 4620, Rev. To M Spec. for Polished Single Crystal Silicon Wafers
Change “Monocrystalline” to “Single Crystal”
Add Profile-Parameter Based Edge Profile Specification (similar to EP6/EP7)
Doc passed at SEMICON Europa
Future M1 revisions to include new Edge Roll Off metrics and possible changes to Decision Trees
NA Silicon Wafer Committee Liaison Report

14. Committee TF
Int’l Terminology TF/Murray Bullis (Materials & Metrology)
Revising M , Terminology for Silicon Technology - ongoing
Other terminologies to be pursued
Surface topography terms
Oxide characterization terms
Edge Defects terms
Needs to form a WG to carry out these edge defects definitions
NA Silicon Wafer Committee Liaison Report

15. Committee TF Int’l Test Methods TF/Dinesh Gupta (STA)
TF submits a SNARF for Revision to SEMI MF , Test Method for Thickness and Thickness Variation of Silicon Wafers
To add 0 deg positioning and nine-point thickness variation measurement
Ballot is expected to be reviewed at NA Spring 2009.
NA Silicon Wafer Committee Liaison Report