1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Registers and Counters
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff The second midterm is this Friday.
Homework 8 is due today.
Homework 9 is out. It is due on Mon Nov 6.
No HW due next Monday

4. Administrative Stuff Midterm Exam #2 When: Friday October 27 @ 4pm.
Where: This classroom
What: Chapters 1, 2, 3, 4 and
The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).

5. Registers

6. Register (Definition)
An n-bit structure consisting of flip-flops

7. Parallel-Access Register

8. 1-Bit Parallel-Access RegisterD Q
Clock In
Out
Load 1

9. 1-Bit Parallel-Access RegisterD Q
Clock In
Out
Load 1
The 2-to-1 multiplexer is used to select whether to load a new value into the D flip-flop or to retain the old value.
The output of this circuit is the Q output of the flip-flop.

10. 1-Bit Parallel-Access RegisterD Q
Clock In
Out
Load 1
If Load = 0, then retain the old value.
If Load = 1, then load the new value from In.

11. 2-Bit Parallel-Access RegisterD Q
Clock
Load 1
In_1
Out_0
Out_1
In_0

12. 2-Bit Parallel-Access Register
Parallel Output D Q
Clock
Load 1
In_1
Out_0
Out_1
In_0
Parallel Input

13. 3-Bit Parallel-Access RegisterD Q
Clock
Load 1
In_2
Out_1
Out_2
In_1
Out_0
In_0
Notice that all flip-flops are on the same clock cycle.

14. 3-Bit Parallel-Access Register
Parallel Output D Q
Clock
Load 1
In_2
Out_1
Out_2
In_1
Out_0
In_0
Parallel Input

15. 4-Bit Parallel-Access Register
Clock
Load D Q 1
In_3
Out_3
In_2
Out_2
In_1
Out_1
In_0
Out_0

16. 4-Bit Parallel-Access Register
Parallel Output
Clock
Load D Q 1
In_3
Out_3
In_2
Out_2
In_1
Out_1
In_0
Out_0
Parallel Input

17. Shift Register

18. A simple shift registerD Q
Clock In
Out 1 2 3 4
[ Figure 5.17a from the textbook ]

19. A simple shift registerD Q
Clock In
Out 1 2 3 4
Positive-edge-triggered
D Flip-Flop

20. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clock m s
Clk

21. A simple shift registerD Q
Clock In
Out 1 2 3 4
D –Flip-Flop D Q
Master
Slave
Clock m s
Clk
Gated D-Latch
Gated D-Latch

22. A simple shift registerD Q
Clock In
Out 1 2 3 4

23. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clk
Clock In

24. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clk
Clock In

25. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clk
Clock In

26. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clk
Clock In

27. A simple shift registerD Q
Clock In
Out 1 2 3 4 D Q
Master
Slave
Clk
Clock In

28. A simple shift registerD Q
Master
Slave
Clk
Clock In

29. A simple shift registerD Q
Master
Slave
Clk
Clock In
Clock

30. A simple shift registerD Q
Master
Slave
Clk
Clock In
Clock

31. A simple shift registerD Q
Master
Slave
Clk
Clock In
Clock

32. A simple shift registerD Q
Master
Slave
Clk
Clock In
Clock

33. A simple shift registerD Q
Clock In
Out t 1 2 3 4 5 6 7 =
(b) A sample sequence
(a) Circuit
[ Figure 5.17 from the textbook ]

34. Parallel-Access Shift Register

35. Parallel-access shift register
[ Figure 5.18 from the textbook ]

36. Parallel-access shift register
When Load=0, this behaves like a shift register.
[ Figure 5.18 from the textbook ]

37. Parallel-access shift register1
When Load=1, this behaves like a parallel-access register.
[ Figure 5.18 from the textbook ]

38. Parallel Load and Enable
Shift Register With
Parallel Load and Enable

39. A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]

40. A shift register with parallel load and enable control inputs
The directions of the input and output lines are switched relative to the previous slides.
[ Figure 5.59 from the textbook ]

41. A shift register with parallel load and enable control inputs
Parallel Input
Parallel Output
[ Figure 5.59 from the textbook ]

42. A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]

43. A shift register with parallel load and enable control inputs1
[ Figure 5.59 from the textbook ]

44. A shift register with parallel load and enable control inputs1
[ Figure 5.59 from the textbook ]

45. A shift register with parallel load and enable control inputs1 1
[ Figure 5.59 from the textbook ]

46. (select one of two 2-bit numbers)
Multiplexer Tricks
(select one of two 2-bit numbers)

47. Select Either A=A1A0 or B=B1B01 s F0 F1 A0 B0 A1 B1

48. Select Either A=A1A0 or B=B1B01 s F0 F1 A0 B0 A1 B1
= A0
= A1

49. Select Either A=A1A0 or B=B1B01 s F0 F1 A0 B0 A1 B1
= B0
= B1

50. (select one of four 2-bit numbers)
Multiplexer Tricks
(select one of four 2-bit numbers)

51. Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D000 01 10 11 A0 B0 C0 D0 F0 A1 B1 C1 D1 F1 1

52. Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0s 00 01 10 11 A0 B0 C0 D0 F0 A1 B1 C1 D1 F1 1
= A0
= A1

53. Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D01 s 00 01 10 11 A0 B0 C0 D0 F0 A1 B1 C1 D1 F1 1
= B0
= B1

54. Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0s 00 01 10 11 A0 B0 C0 D0 F0 A1 B1 C1 D1 F1 1
= C0
= C1

55. Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D000 01 10 11 A0 B0 C0 D0 F0 A1 B1 C1 D1 F1 1
= D0
= D1

56. Register File

57. one read port, and one write enable line.
Complete the following circuit diagram to implement a register file with four 2-bit registers, one write port,
one read port, and one write enable line.

59. Register 0
Register 1
Register 2
Register 3

60. Register A
Register B
Register C
Register D

61. Register A
Register B
Register C
Register D A1 A0 B1 B0 C1 C0 D1 D0

62. Register A Register B Register C Register D A1 A0 B1 B0 C1 C0 D1 D0
In1
In0

63. Register A Register B Register C Register D A1 A0 B1 B0 C1 C0 D1 D0
In1
In0
Write_enable
Write_address_0
Write_address_1

64. Register A Register B Register C Register D A1 A0 B1 B0 C1 C0 D1 D0
In1
In0
Write_enable
Write_address_0
Write_address_1

65. Register A Register B Register C Register D A1 A0 B1 B0 C1 C0 D1 D0
In1
In0
Out1
Out0
Write_enable
Write_address_0
Write_address_1
Read_address_1
Read_address_0

66. Register A Register B Register C Register D A1 A0 B1 B0 C1 C0 D1 D0
In1
In0
Out1
Out0
Write_enable
Write_address_0
Write_address_1
Read_address_1
Read_address_0
Clock

67. A1 A0 B1 B0 C1 C0 D1 D0 In1 In0 Out1 Out0 Clock Write_address_0
Write_enable
Write_address_0
Write_address_1
Read_address_1
Read_address_0
Clock

68. Another Register File

69. Register File Register file is a unit containing r registersWA WR
RA2
RA1
LD_DATA
DATA1
DATA2
Register file is a unit containing r registers
r can be 4, 8, 16, 32, etc.
Each register has n bits
n can be 4, 8, 16, 32, etc.
n defines the data path width
Output ports (DATA1 and DATA2) are used for reading the register file
Any register can be read from any of the ports
Each port needs a log2r bits to specify the read address (RA1 and RA2)
Input port (LD_DATA) is used for writing data to the register file
Write address is also specified by log2r bits (WA)
Writing is enabled by a 1-bit signal (WR)

70. Register File: Exercise
Suppose that a register file
contains 32 registers
width of data path is 16 bits
(i.e., each register has 16 bits)
How many bits are there for each of the signals?
RA1
RA2
DATA1
DATA2 WA
LD_DATA WR
Reg
File WA WR
RA2
RA1
LD_DATA
DATA1
DATA2 5 16 1

71. Register file design
We will design an eight-register file with 4-bit wide registers
A single 4-bit register and its abstraction are shown below
We have to use eight such registers to make an eight register file
How many bits are required to specify a register address? LD
Clock Q0 Q1 Q2 Q3 D3 D2 D1 D0 D Q P 1
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Clock LD
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Clk LD

72. Reading Circuit
A 3-bit register address, RA, specifies which register is to be read
For each output port, we need one 8-to-1 4-bit multiplier
8-to-1 4-bit multiplex
RA1
DATA1
RA2
DATA2
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Clk
LD0
LD1
LD7
Register
Address
111
001
000

73. Adding write control to register file
To write to any register, we need the register's address (WA) and a write register signal (WR)
A 3-bit write address is decoded if write register signal is present
One of the eight registers gets a LD signal from the decoder
8-to-1 4-bit multiplex
RA1
DATA1
RA2
DATA2
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Clk
LD0
LD1
LD7
LD_DATA WA 3 to 8 D e c o d r WR
111
001
000
LD2

74. Register File
(More Examples)

75. Register File [

76. [http://fourier. eng. hmc. edu/e85_old/lectures/digital_logic/node19[

77. This is a more detailed diagram showing only 2 of the bits in 4 of the registers:[

78. [http://www. eecg. toronto[

79. Counters

80. T Flip-Flop (circuit and graphical symbol)
[ Figure 5.15a,c from the textbook ]

81. The output of the T Flip-Flop divides the frequency of the clock by 2

82. The output of the T Flip-Flop divides the frequency of the clock by 21

83. A three-bit down-counter
[ Figure 5.20 from the textbook ]

84. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.20 from the textbook ]

85. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.20 from the textbook ]

86. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.20 from the textbook ]

87. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
[ Figure 5.20 from the textbook ]

88. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
least
significant
most

89. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q0 toggles
on the positive
clock edge

90. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q1 toggles
on the positive
edge of Q0

91. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q2 toggles
on the positive
edge of Q1

92. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
The propagation delays get longer

93. A three-bit up-counter
[ Figure 5.19 from the textbook ]

94. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.19 from the textbook ]

95. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.19 from the textbook ]

96. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.19 from the textbook ]

97. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

98. A three-bit up-counter
[ Figure 5.19 from the textbook ] T Q
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
least
significant
most

99. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The count
is formed
by the Q’s
[ Figure 5.19 from the textbook ]

100. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The toggling
is done
by the Q’s

101. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q0 toggles
on the positive
clock edge

102. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q1 toggles
on the positive
Edge of Q0

103. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q2 toggles
on the positive
edge of Q1

104. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The propagation delays get longer

105. A three-bit up-counter1 T Q T Q T Q
Clock Q Q Q Q Q Q 1 2
The propagation delays get longer
(a) Circuit
Clock Q Q 1 Q 2
Count 1 2 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

106. Synchronous Counters

107. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

108. A four-bit synchronous up-counter
The propagation delay through all AND gates combined must
not exceed the clock period minus the setup time for the flip-flops
[ Figure 5.21 from the textbook ]

109. A four-bit synchronous up-counterQ
Clock 1 2
(a) Circuit
Count 3 5 9 12 14
(b) Timing diagram 4 6 8 7 10 11 13 15
[ Figure 5.21 from the textbook ]

110. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
[ Table 5.1 from the textbook ]

111. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
T0= 1
T1 = Q0
T2 = Q0 Q1
[ Table 5.1 from the textbook ]

112. A four-bit synchronous up-counter
T1 = Q0
T2 = Q0 Q1
[ Figure 5.21 from the textbook ]

113. In general we have T0= 1 T1 = Q0 T2 = Q0 Q1 T3 = Q0 Q1 Q2 …
Tn = Q0 Q1 Q2 …Qn-1

114. Synchronous v.s. Asynchronous Clear

115. 2-Bit Synchronous Up-Counter (without clear capability)1 T Q
Clock Q0 Q1

116. 2-Bit Synchronous Up-Counter (with asynchronous clear)1 T Q
Clock
Clear_n Q0 Q1

117. 2-Bit Synchronous Up-Counter (with asynchronous clear)1 D Q
Clock
Clear_n Q0 Q1
This is the same circuit but uses D Flip-Flops.

118. 2-Bit Synchronous Up-Counter (with synchronous clear)1 D Q
Clock
Clear_n Q0 Q1
This counter can be cleared only on the positive clock edge.

119. Adding Enable Capability

120. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

121. Inclusion of Enable and Clear CapabilityQ
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

122. Inclusion of Enable and Clear Capability
This is the new thing relative to
the previous figure, plus the clear_n line T Q
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

123. Providing an enable input for a D flip-flop
[ Figure 5.56 from the textbook ]

124. Synchronous Counter
(with D Flip-Flops)

125. A four-bit counter with D flip-flops
[ Figure 5.23 from the textbook ]

126. Counters with Parallel Load

127. A 4-bit up-counter with D flip-flops
[ Figure 5.23 from the textbook ]

128. A 4-bit up-counter with D flip-flops
T flip-flop
T flip-flop
T flip-flop
T flip-flop
[ Figure 5.23 from the textbook ]

129. Equivalent to this circuit with T flip-flops
Enable T Q T Q T Q T Q
Clock Q Q Q Q

130. Equivalent to this circuit with T flip-flopsZ
Enable T Q T Q T Q T Q
Clock Q Q Q Q
But has one extra output called Z, which can be used to
connect two 4-bit counters to make an 8-bit counter.
When Z=1 the counter will go 0000 on the next clock edge, i.e.,
the outputs of all flip-flops are currently 1 (maximum count value).

131. Counters with Parallel Load

132. A counter with parallel-load capability
[ Figure 5.24 from the textbook ]

133. How to load the initial count value1
Set the initial count on
the parallel load lines
(in this case 5).

134. How to zero a counter 1 1 Set "Load" to 1, to open the1
Set "Load" to 1, to open the
"1" line of the multiplexers. 1

135. How to zero a counter 1 1 1 When the next positive edge of1 1
When the next positive edge of
the clock arrives, the outputs
of the flip-flops are updated. 1

136. Reset Synchronization

137. Motivation An n-bit counter counts from 0, 1, …, 2n-1
For example a 3-bit counter counts up as follow
0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …
What if we want it to count like this
0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, …
In other words, what is the cycle is not a power of 2?

138. What does this circuit do?
[ Figure 5.25a from the textbook ]

139. A modulo-6 counter with synchronous reset
Enable Q 1 2 D
Load
Clock 3 4 5
Count
(a) Circuit
(b) Timing diagram
[ Figure 5.25 from the textbook ]

140. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
[ Figure 5.26 from the textbook ]

141. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
The number 5 is displayed
for a very short amount of time
[ Figure 5.26 from the textbook ]

142. Questions?

143. THE END