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VDD Vin+ CL Vin- Vb3 folded cascode amp Vb2 Vb1 Vb4 Vb5.

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Presentation on theme: "VDD Vin+ CL Vin- Vb3 folded cascode amp Vb2 Vb1 Vb4 Vb5."— Presentation transcript:

1 VDD Vin+ CL Vin- Vb3 folded cascode amp Vb2 Vb1 Vb4 Vb5

2 Output swing range and input common mode range are now decoupled.
OSR: VDD-4Veff ICMR: 2Veff+Vt1 to VDD-Veff +Vt1 VDD-3Veff But, if Vic cannot exceed VDD, ICMR: 2Veff+Vt1 to VDD VDD-2Veff-Vt1

3 D1 connects to G2, two stages
VDD VDD VDD VDD two stage CS amplifier CS amplifier with a source follower buffer

4 VDD VDD VDD Vx Vx Same as above, only T2 is pMOS Connecting S1 to D2 makes ro really small buffer or output stage

5 VDD Vbp Vbn vin vo

6 Miller equivalent circuit
I2 =Y(V2-V1) =Y(V2+V2/A) =(1+1/A)YV2 Y2=(1+1/A)Y Y Chapter 4 Figure 15 I1=I=Y(V1-V2) =Y(V1+AV2) =(1+A)YV1 Y1=(1+A)Y

7 The above is proven by assuming constant A.
But in reality, A depends on Y and connection. Correct use of Miller is quite tricky!

8 v2 = -Av1 v2 Agm1R2 This is for DC.

9 But this is missing the positive zero: z1 = +gm1/Cgd1
v1/vin=1/(1+sRs(Cgs1+(1+gm1R2 )Cgd1)) vo/v1= -gm1/(G2 + s(C2 +Cgd1)) Multiply: vo/vin= -gm1/{(G2 + s(C2 +Cgd1))(1+sRs(Cgs1+(1+gm1R2 )Cgd1))} But this is missing the positive zero: z1 = +gm1/Cgd1  Cgd1 A better approach: first set Rs=0, find TF from gate to vo, as we did before; then use Miller effect, find TF from vin to v1 (left circuit); then multiply together to get TF from vin to vo.  vo/vin = (sCgd1 -gm1)/{(G2 + s(C2 +Cgd1))(1+sRs(Cgs1+(1+gm1R2 )Cgd1))}

10 g'm=gm1+gs11.2gm1 KCL at vo: -g’mvs+(vo-vs)gds+vo(GL+sC2)=0 vo/vs=(g’m+gds)/(gds+GL+sC2)

11 Zero value time constant:
If a TF=n(s)/d(s) has only real poles d(s)=(1+t1s)(1+t2s)(1+t3s)… =1+(t1+t2+t3+…)s + (t1t2+t2t3+…)s2+… For low frequency, s small, we have d(s)  1+(t1+t2+t3+…)s Hence the lowest freq pole is approximately p1  -1/(t1+t2+t3+…) This only good for low freq, and real poles.

12 Application: Perform series/parallel simplification For each remaining capacitor, find resistance it sees by: Short V-source, open I-source, open other caps teff = R1C1+R2C2+…

13 C2 is CL||Cdb1||Cdb2 R2 is rds1||rds2 Cgs1 sees Rs, C2 sees R2 For Cgd1, more complex.

14 Resistance seen by Cgd1 can be found by applying a test v3 across Cgd1, finding the resulting current i3, and using R3=v3/i3 R3 = R2 + (1+gm1R2)*Rs teff=RsCgs1+R2C2+R2Cgd1+ (1+gm1R2)*RsCgd1

15 4.2.6 If vin is v-source, Small signal model Should be: ~

16 VDD VDD M7 M5 Vyy Vxx M8 M6 vo- vo+ CL M3 M4 Vbb CL M1 M2 vin+ vin- Vs

17 VDD VDD VDD Rb M2 Vbb CL M1 Vin Vo Vo Both have the same small signal model


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