1. ECE 5571 Digital System Design 1
Message Decoding
Design & Simulation
Jim Freebourn
2/22/2019
ECE 5571 Digital System Design 1

2. ECE 5571 Digital System Design 1
Introduction
This message decoding design describes a segment of a data storage system in terms of the AHPL language with logic verification using VHDL with supporting tools.
Jim Freebourn
Electrical Engineer in the Control Engineering Division at the Harris Corporation
2/22/2019
ECE 5571 Digital System Design 1

3. ECE 5571 Digital System Design 1
Project Proposal
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4. ECE 5571 Digital System Design 1
Topics of Discussion
The main focus of this project describes the section of a decoding system used to store data at a specified memory location.
Each message contains 4-bytes of information
Memory section uses the concept of memory mapping
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5. Message Decoding Digital Design
Message Decoding Concept
AHPL Design Methodology
Graphical Design using VHDL
Hierarchical Design Environment using Visual Elite by Innoveda Inc.
Logic Simulations
Logic verification using NCLaunch by Cadence Design Systems, Inc.
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6. Message Decoding Concept
Concept Requirements:
An FPGA must store control circuit parameters to operate the Phase Array Circuitry .
Amplifier On/Off mask
X & Y Element Location
Phase Shifter Calibration Data
Memory Map Concept
Panel Message
Header Information
Memory Address
Data
Message Confirmation Byte (Trailer)
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7. ECE 5571 Digital System Design 1
Message Decoding State Machine
(7-States Identified)
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8. ECE 5571 Digital System Design 1
Memory Map Concept
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9. ECE 5571 Digital System Design 1
Memory Map Concept
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10. ECE 5571 Digital System Design 1
Panel Header Message
Global Msg Bit – Signifies message type If this bit is 0 then the D6-D0 are actually defined as shown
Counter – Indicates how many bytes will follow the header. The 4-bit counter will contain a code that indicates a number of bytes expected
Panel Address – Indicates the panel identifier
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11. Panel Message Structure
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12. Graphical Design using VHDL
Serial Decoder to Dual Port Memory
Message Decoding Layer
Panel Message Module
Panel Message Block
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13. ECE 5571 Digital System Design 1
Serial Decoder to Dual Port Memory
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14. ECE 5571 Digital System Design 1
Message Decoding
Layer
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15. ECE 5571 Digital System Design 1
Panel Message Model
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16. ECE 5571 Digital System Design 1
Panel Message Block
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17. ECE 5571 Digital System Design 1
Logic Simulations
Logic Verification
Memory Storage Validation
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18. ECE 5571 Digital System Design 1
Logic Verification
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19. ECE 5571 Digital System Design 1
Logic Verification
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20. Memory Storage Validation
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21. Memory Storage Validation
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22. AHPL Design Methodology
Development of a Design
Messaging Concept
STEP sequence to monitor the output process STATES
7 STATES
IDLE, GETMESS, NEXTBYTE, CHECK, DECODE, WAIT, RESET
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23. Development of a Design
Development of a Design (pg 103) in the Digital Systems “Hardware Organization and Design Third Edition”, Fredrick J. Hill & Gerald R. Peterson
It is not always easy to think through a design concept while representing it only in the form of a one-dimensional language or list of branches and transfers (AHPL).
A two-dimensional format or a flowchart language sometimes provides a much better vehicle for guiding the thought process through the development of an algorithm.
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24. Development of a Design
A recommended procedure will be to use a flowchart as a starting point in the development of a complete AHPL description.
The example 4.3 on pg 104 in the book begins with a word description of the design problem and then illustrates the development of an AHPL control sequence.
A flowchart is used to assist in the process.
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25. ECE 5571 Digital System Design 1
Message Concept
Message
Stream
Valid byte
based on
parity, start,
& stop bits
Panel
State
Machine
Header
Memory Address
Data
Confirmation Byte
Header routes the
Message stream to the
correct state machine
for decoding.
State Machine
Decodes Message
Memory Address
Data
Check Confirmation
Valid message
based on
confirmation
byte
Store data in memory
at specified memory
location
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26. ECE 5571 Digital System Design 1
Message Concept
Transfer Data to Registers
Index n and m
Dual Port
Block Memory
mem8x32 X
(DATAOUT) DR
(AMPDATA) AR
(AMPSEL) 8
LOWERADDR
UPPERADDR
CHECKPANELMESS (If valid process will store data to memory)
K = 2
K = 3
K = 4
K = 5
WRITE
(AMPVALCAPTURED)
Transfer Data to DR
Index nbit and mbit
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27. ECE 5571 Digital System Design 1
Step Sequence
IDLE STATE – STEP(3 – 9)
GETMESS STATE – STEP(10-18)
NEXTBYTE STATE – STEP(19-23)
CHECK STATE – STEP(24-28)
DECODE STATE – STEP(29 – 36)
WAIT STATE – STEP(37)
RESET STATE – STEP(41)
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28. ECE 5571 Digital System Design 1
The basic idea is to transfer a data stream that represents the memory address, memory data, and a message confirmation code.
The STEP allows tracking the process in the output file.
Attempt to use ZEROCNTL to control state processing
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29. ECE 5571 Digital System Design 1
IDLE STATE (step 3 - 9)
COUNTER set to CNT (4)
N & M Set to 56 decimal. Transfer 7-bytes.
Increment counter until ZEROCNTL reaches COUNTER equals 6.
Reset ZEROCNTL. Set DECODE INDEX (4)
Set NBIT & MBIT to N & M.
Decrement NBIT by 1. DATA(NBIT:MBIT)
DATA(55:MBIT)
Decrement MBIT by 8. DATA(NBIT:MBIT)
DATA(55:48); ZEROCNTL ^(&(111)) next step.
&(111) = 1 not this equals 0 stop loop
&(101) = 0 not this equals 1 go to step 7
Decrement N by 1.
Decrement M by 8.
ZEROCNTL ^(&(111)) next step.
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30. ECE 5571 Digital System Design 1
GETMESS STATE (step )
The getmess state is controlled by two 4-bit counters K and COUNTER.
K=0000 / 12, k=0001 / 13, k=0010 / 14
K=0011 / 15, k=0100 / 16, k=0101 / 17
K=COUNTER / 18
Transfer Data to Lower Address
Transfer Data to Upper Address
1st Data Byte
2nd Data Byte
Step 7:
&(111) = 1 not this equals 0 stop loop
&(101) = 0 not this equals 1 go to step 7
Step 10:
Step 10 is not shown: This step checks getmess, panelsel, and endata (enable data)
These are just set by projdata file.
3rd Data Byte
4th Data Byte
Transfer Message Confirmation
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31. NEXT BYTE STATE (step 19 – 23)
K counter is incremented
Transfer step 20: if K and Counter are not equal and N is not zero.
Decrement N by 8
Reset ZEROCNTL Counter
Decrement M by 8
&(111) = 1 not this equals 0 stop loop
&(101) = 0 not this equals 1 go to step 7
Transfer Upper & Lower Address to ADDRMEM Register
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32. ECE 5571 Digital System Design 1
Step 19 increments K; this means that N and M will be decremented before data is transferred.
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33. ECE 5571 Digital System Design 1
Check State (24 – 28)
Max address is 32. If there is a 1 in bits 0:10 then 32 is exceeded.
Msg Validity is checked
Address Boundary is the Max address minus the beginning address. This indicates the amount of data space available.
Max 32 – ADDRMEM = ADDRBOUNDARY.
(32 – 15 = 17-bytes available to store 4-bytes)
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34. ECE 5571 Digital System Design 1
CHECK STATE
Incrementing up addrtemp until equal with addrmem. When addrtemp = addrmem then addrboundary stops decrementing down from maximum address.
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35. ECE 5571 Digital System Design 1
Decode State ( )
Max address check & Address Boundary check.
If 1 is in 0:11 then the address boundary exceeded. Reset.
DECODEINDEX
0100 / 33, 0011 / 34
0010 / 35, 0001 / 36
0000 / 41 Reset
Store Amplifier AMPSEL address
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36. Wait (37) & Reset States (41)
Decrement the DECODEINDEX Counter & Reset the AMPVALCAPTURED
Reset Registers and Counters
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37. ECE 5571 Digital System Design 1
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38. Summary (Trade Study Results)
No concrete design method using AHPL. Seems to be more of a learning tool for investigating basic logic devices.
The AHPL software program only supports basic logic. Exploring incrementing, decoding, encoders, comparators …
CLUNIT (Increment & decrement) limited to 8-bit and user defined CLUNITs not supported
Registers limited to holding 28-bits
No Delay not supported
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39. ECE 5571 Digital System Design 1
Suggestion
Use VHDL
Digital Systems Design Using VHDL, Charles H. Roth, Jr. ~$100
Features:
Teaches the use of VHDL in the digital design process – both digital design concepts and VHDL are covered simultaneously.
Teaches the use of VHDL for modeling, simulating, and synthesizing digital systems.
Many vendors supply tools for VHDL coding.
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40. ECE 5571 Digital System Design 1
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