1. ESE534 Computer Organization
Day 6: February 1, 2012
Energy, Power, Reliability
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2. Today Energy tradeoffs Voltage limits and leakage Variations
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3. At Issue Many now argue energy will be the ultimate scaling limit
(not lithography, costs, …)
Proliferation of portable and handheld devices
…battery size and life biggest issues
Cooling, energy costs may dominate cost of electronics
Even server room applications
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4. Preclass 1 1GHz case 2GHz case Voltage? Energy per Operation?
Power required for 2 processors?
2GHz case
Power required for 1 processor?
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5. tgd=Q/I=(CV)/I Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2 Energy and Delay
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6. Energy/Delay Tradeoff
EV2
tgd1/V
We can trade speed for energy
E×(tgd)2 constant
¿gd=(CV)/I
Id,sat (Vgs-VTH)2
Martin et al. Power-Aware Computing, Kluwer 2001
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7. Area/Time Tradeoff Also have Area-Time tradeoffs
HW2 spatial vs temporal multipliers
See more next week
Compensate slowdown with additional parallelism
…trade Area for Energy  Architectural Option
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8. Question By how much can we reduce energy? What limits us?
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9. Challenge: Power
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10. Origin of Power Challenge
Limited capacity to remove heat
~100W/cm2 force air
1-10W/cm2 ambient
Transistors per chip grow at Moore’s Law rate = (1/F)2
Energy/transistor must decrease at this rate to keep constant power density
P/tr  CV2f
E/tr  CV2
…but V scaling more slowly than F
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11. Energy per Operation Ctotal = # transistors × Ctr
Ctr scales (down) as F
# transistors scales as F-2
…ok if V scales as F…
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12. ITRS Vdd Scaling: More slowly than F
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13. ITRS CV2 Scaling: More slowly than (1/F)2
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14. Origin of Power Challenge
Transistors per chip grow at Moore’s Law rate = (1/F)2
Energy/transistor must decrease at this rate to keep constant
E/tr  CV2
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15. Historical Power Scaling
[Horowitz et al. / IEDM 2005]
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16. Microprocessor Power Density
Watts
The Future of Computing Performance: Game Over or Next Level?
National Academy Press, 2011
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17. Intel Power Density
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18. Impact Power Limits Integration Source: Carter/Intel 18
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19. Impact Power density is limiting scaling
Can already place more transistors on a chip than we can afford to turn on!
Power is potential challenge/limiter for all future chips.
Only turn on small percentage of transistors?
Operate those transistors as much slower frequency?
Find a way to drop Vdd?
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20. How far can we reduce Vdd?
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21. Limits Ability to turn off the transistor Parameter Variations
Noise (not covered today)
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22. MOSFET Conduction
From:
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23. Transistor Conduction
Three regions
Subthreshold (Vgs<VTH)
Linear (Vgs>VTH) and (Vds < (Vgs-VTH))
Saturation (Vgs>VTH) and (Vds > (Vgs-VTH))
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24. Ids,sat=(mCOX/2)(W/L)(Vgs-VTH)2
Saturation Region
(Vgs>VTH)
(Vds > (Vgs-VTH))
Ids,sat=(mCOX/2)(W/L)(Vgs-VTH)2
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25. Linear Region Ids,lin=(mCOX)(W/L)((Vgs-VTH)Vds-(Vds)2/2) (Vgs>VTH)
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26. Subthreshold Region (Vgs<VTH) [Frank, IBM J. R&D v46n2/3p235]
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27. Operating a Transistor
Concerned about Ion and Ioff
Ion drive (saturation) current for charging
Determines speed: Tgd = CV/I
Ioff leakage current
Determines leakage power/energy:
Pleak = V×Ileak
Eleak = V×Ileak×Tcycle
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28. Leakage To avoid leakage want Ioff very small Switch V from Vdd to 0
Vgs in off state is 0 (Vgs<VTH)
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29. Leakage Leakage limits VTH in turn limits Vdd S90mV for single gate
S70mV for double gate
For lowest leakage, want S small, VTH large
4 orders of magnitude IVT/IoffVTH>280mV
Leakage limits VTH in turn limits Vdd
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30. Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2
How maximize Ion/Ioff ?
Maximize Ion/Ioff – for given Vdd ? EswCV2
Get to pick VTH, Vdd
Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2
Id,lin=(mCOX)(W/L)(Vgs-VTH)Vds-(Vds)2/2
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31. Preclass 2 E = Esw + Eleak Eleak = V×Ileak×Tcycle EswCV2
Ichip-leak = Ndevices ×Itr-leak
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32. Preclass 2 Eleak(V) ? Tcycle(V)?
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33. In Class Assign calculations Collect results on board
SIMD – each student computes for a different Voltage
Collect results on board
Should go quick once students have time to calculate
Identify minimum energy point and discuss
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34. Graph for In Class
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35. Impact
Subthreshold slope prevents us from scaling voltage down arbitrarily.
Induces a minimum operating energy.
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36. Challenge: Variation
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37. Statistical Dopant Count and Placement
[Bernstein et al, IBM JRD 2006]
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38. Vth Variability @ 65nm [Bernstein et al, IBM JRD 2006]
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39. (From ITRS prediction)
Variation
Fewer dopants, atoms  increasing Variation
How do we deal with variation?
% variation in VTH
(From ITRS prediction) 40
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40. Impact of Variation? Higher VTH? Lower VTH?
Not drive as strongly  slower
Id,sat (Vgs-VTH)2
Lower VTH?
Not turn off as well  leaks more
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41. Variation Ion,min=Ion(Vth,max) Margin for expected variation
Must assume VTH can be any value in range
Ion,min=Ion(Vth,max)
Id,sat (Vgs-VTH)2
Vgs = Vdd
Probability Distribution
VTH
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42. Margining Ion,min=Ion(Vth,max)
Must raise Vdd to increase drive strength
Increase energy
Ion,min=Ion(Vth,max)
Id,sat (Vgs-VTH)2
Vgs = Vdd
Probability Distribution
VTH
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43. Variation Increasing variation forces higher voltages
On top of our leakage limits 44
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44. Variations Margins growing due to increasing variation
Probability Distribution
Delay
New
Old
Margins growing due to increasing variation
Margined value may be worse than older technology?
One key issue showing up today is increased variation.
(We noted on slide 2 that decreasing number of dopants directly leads to increased variance in device characterstics.)
As the variation increases, so must our margins. This diminishes the benefit we see from advanced technology.
The diagram shows that the mean device behavior for a smaller feature size technology gets better (i.e. lower delay) as expected. This is what we’re tracking on the ideal (black) curve.
However, the variance for the advanced (smaller feature size) technology is larger. This means that after we apply margining for yield and worst-case path effects, the chip-level benefit is lower. …and so, the larger variance means we do not see the full, ideal scaling in device performance (hence the purple curve).
For DoD system, we often require greater margins to accommodate wider operating scenarios and/or as part of derating for harsh environment operation. This greater margining leads to even a greater degradation of performance. In the extreme, this might lead to inversion where the new technology, with margining, is actually worse than the older technology with lower variation.
In practice, it’s unlikely that this inversion will arise entirely based on this effect alone, but this effect is composed with the earlier effects of defect and fault mitigation and the composite effect can likely lead to this inversion.
The solution here is to go away from worst-case margined designs. With the methodologies proposed here, we make the designs tolerant to failures-in-the-middle. That allows us to detect the uncommon cases where the device fails to meet timing and recover. This allows us to achieve performance on the red curve.
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45. End of Energy Scaling? Black nominal Grey with variation
[Bol et al., IEEE TR VLSI Sys 17(10):1508—1519]
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46. Chips Growing
Larger chips (billions of transistors)  sample further out on distribution curve
From:
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47. Admin Homework due Monday Reading for Monday on web
Section 3.5 has changed
Please grab updated copy
Reading for Monday on web
André back on Monday
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48. Big Ideas Continued scaling demands Can trade time for energy
… area for energy
Variation and leakage limit voltage scaling
Power major limiter going forward
Can put more transistors on a chip than can switch
Continued scaling demands
Deal with noisier components
High variation
… other noise sources
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