1. Scrambler Mismatch Correction Using the MAC FEC
Month 2002
doc.: IEEE /429r0
July 2002
Scrambler Mismatch Correction Using the MAC FEC
Mark Webster, Mike Seals,
Steve Halford, Paul Chiuchiolo
Intersil
July 2002
Mark Webster, Intersil
Mark Webster, Intersil

2. Month 2002
doc.: IEEE /429r0
July 2002
Overview
A forward-error-correction (FEC) option exists in the e draft which uses an 8-octet correcting Reed-Solomon (255,239) block code.
If the a PHY demodulator makes any bit-errors in the received scrambler seed (state), the FEC blocks will all error. (IEEE /050 and –02/221)
A nice solution to this problem has been proposed (IEEE /325)
Unfortunately, this solution weakens the performance of the Reed-Solomon FEC thru error multiplication
Herein, a simple technique is presented which restores a performance to 10-9 frame-error-rates
No additional overhead is added to the FEC frames to make this technique work
The power of the FEC itself is used to determine the scrambler mismatch
Mark Webster, Intersil
Mark Webster, Intersil

3. July 2002
Solution Constraints
The MAC and PHY cannot coordinate. The existing interface must remain as is.
The fix cannot be made in the PHY
Systematic property must remain, so e radios w/o the FEC option can process PHY-error-free frames
Legacy radio’s (pre e) must be able to read the MAC header without any knowledge of e
Mark Webster, Intersil

4. Desirable Solution Features
July 2002
Desirable Solution Features
Works at frame-error-rates to 10-9 (IEEE /40 and /377)
Works for short frames and long frames
Introduces no extra frame overhead
Solution works for all PHY’s
Prevents MAC from being PHY dependent
Must fix the a problem (and g’s OFDM)
Must not introduce a new problem to other PHY’s
The MAC-level fix should be PHY blind
Low complexity, low latency, little buffering
Mark Webster, Intersil

5. 802.11e FEC Frame Format All numbers are in octets Frame Checksum MAC
July 2002
802.11e FEC Frame Format
All numbers are in octets
Frame
Checksum
MAC
Header
Variable
Length
Frame Body
4 to
FEC
Parity
Octets
MAC Header FEC Block: (48,32) shortened by m = 207
Normal Data FEC Block: (224,208) shortened by m = 31
Mark Webster, Intersil

6. An Existing Proposed Solution
July 2002
An Existing Proposed Solution
Mark Webster, Intersil

7. A Proposed Solution Presented in Sydney, May 2002
July 2002
A Proposed Solution
Presented in Sydney, May 2002
Doc.: IEEE /325r0
Title: Dual Precoding with FEC Packets
Authors: Chris Heegard, Lior Ophir, Richard Williams and Sid Schrum
Moving average bit-filters g(D) and recursive bit-filters 1/g(D) are used, exploiting the properties of the a scrambler mismatch sequence
Mark Webster, Intersil

8. Solution Presented in Sydney (doc:IEEE 802.11-02/325r0)
July 2002
Solution Presented in Sydney (doc:IEEE /325r0)
Legacy Stations
See Systematic Data
(MAC Header)
Scrambler
Mismatch Removed
x(D)
Equivalent
802.11a PHY
Self-Sync
FIR
FIR
IIR
IIR
x(D)
x(D)
FEC
Encode
FEC
Decode
g(D)
1/g(D) +
g(D)
1/g(D)
D(D)
IIR
1/g(D)
Initial state
No mismatch: state =0
Mismatch: state ~=0
x2(D)=0
Mark Webster, Intersil

9. Issues With Sydney’s Solution
July 2002
Issues With Sydney’s Solution
Precoding weakens the MAC FEC (IEEE r3-E)
The receive self-synchronizing FIR filter g(D) causes error multiplication
Up to 3 * (Number of bit errors)
Up to 2 * (Number of octet errors)
Instead of the Reed-Solomon (255,239) correcting 8 octets in error, it can be limited by 4 octets in error at the PHY output
The FEC effectiveness is lower-bounded to half the design goal for independent octet errors
Mark Webster, Intersil

10. Bit-Error Multiplication Problem
July 2002
Bit-Error Multiplication Problem
FIR Bit-Filter, g(D)
RX PHY OUTPUT
TO FEC DECODER + +
Input Bit
Error Pattern
Output Bit
Error Pattern D4 D3
One input error
3 output errors
For every input bit error,
up to 3 output bits errors can occur.
Mark Webster, Intersil

11. Octet-Error Multiplication Problem
July 2002
Octet-Error Multiplication Problem
FIR Bit-Filter, g(D)
RX PHY OUTPUT
TO FEC DECODE + +
Input Octet
Error Pattern
Output Bit
Error Pattern D4 D3
One octet
in error
2 octets in error
For every input octet in error,
up to 2 output octets can be in error.
Mark Webster, Intersil

12. July 2002
PHY Error Events
1 and 2 Mbps DSSS & FH PHY’s experience random bit errors
5.5 Mbps CCK experiences nibble errors (4 bit chunks)
11 Mbps CCK experiences octet errors
OFDM experiences some form of error clustering due to Viterbi trace-back re-sync behavior (see r0-E)
Mark Webster, Intersil

13. July 2002
A New Idea
Mark Webster, Intersil

14. July 2002
A New Idea
MAC header is short compared to full FEC blocks (32 vs. 208 data octets), so the MAC header is much more robust.
Therefore, use dual-precoding on the MAC header only.
Dual-precoding enables FEC decoding in the face of scrambler mismatch
The power of the FEC can then be used to compute the scrambler mismatch reliably
Mark Webster, Intersil

15. New Solution’s Frame Format
July 2002
New Solution’s Frame Format
Use dual precoding only on the MAC header
Little performance loss because MAC header is so short
No additional overhead added to frame
Frame
Checksum
MAC
Header
Variable
Length
Frame Body
4 to
Use dual precoding
MAC computes scrambler mismatch
Correct scrambler mismatch
Switch to pure FEC
Do not use precoding here
Mark Webster, Intersil

16. New Solution’s Block Diagram
July 2002
New Solution’s Block Diagram
Compute
Scrambler
Mismatch
Self-Sync
FIR
FIR
IIR
IIR
FEC
Encode
FEC
Decode
x(D)
g(D)
1/g(D)
g(D)
1/g(D) M U X M U X P H Y M U X M U X
x(D)
FEC
Encode
FEC
Decode +
Scrambler
Correct
Jam State
Tx MUX Control
MAC HDR Blk: Upper Path
Data Blk: Lower Path
Rx MUX Control
MAC HDR Blk: Upper Path
Data Blk: Lower Path
Mark Webster, Intersil

17. Computing Scrambler Mismatch: Basic Concept
July 2002
Computing Scrambler Mismatch: Basic Concept
Only exists for a OFDM
And g OFDM
Scrambler
Mismatch
Noise
Bit
Errors
Desired
Data
Strip
Data
Strip
Errors
Any 7 error-free
bits specify state.
Location specifies
state phase offset.
x(D)+D(D)+E(D)
D(D)
PHY
D(D)+E(D) + +
x(D)
E(D)
Recovered
Data
Error
Pattern
Provided by FEC Decoder
Mark Webster, Intersil

18. Compute Scrambler Mismatch Using MAC Header
July 2002
Compute Scrambler Mismatch Using MAC Header
Scrambler
Mismatch
Strip
Errors
Desired
Data
Strip
Data
Bit
Errors
Scrmblr
Mismatch
State
D(D)
x(D)+D(D)+E(D)
D(D)+E(D)
Unique State
Any 7 error-free
bits (address)
Plus, location in frame (index) + +
Recovered Data
g(D)x(D)
Self-Sync
FIR
Rx Data
x(D)
IIR
FEC
Decode
PHY
g(D)
1/g(D)
g(D)x(D)
+d(D)
+g(D)E(D)
Error Pattern
d(D)+g(D)E(D)
Trimmed
g(D)E(D)
Trimmed
E(D)
Trim Input
To Start at
Zero State
1/g(D)
IIR
d(D): Self-Sync start-up errors.
Occur only in first 7 bits.
(first octet).
Jam Error Pattern
State=0
Mark Webster, Intersil

19. July 2002
802.11a/802.11g OFDM Performance
Short frame
Long frame
Performance reaches 10-9 frame error rates
No degradation with 7 FEC payload blocks
Small degradation with 1 FEC payload block
All curves were generated using
the technique described in
r0-E
Red and black (w/o MA filter)
Blue (w/ MA filter)
Error Rate vs. Bit SNR
Mark Webster, Intersil

20. Performance with 802.11b (mandatory modes)
July 2002
Performance with b (mandatory modes)
Short frame
Long frame
Uncorrelated (i.i.d.) octet errors
Some performance loss exists if used on low-error-rate b packets
Some MAC may choose to not be PHY blind?
Black and red curves were generated
using the technique described in
r0-E.
Blue curve was simulation generated.
(Scrambler mismatch, precoding, FEC)
Error Rate vs. Byte Error Rate
Mark Webster, Intersil

21. July 2002
Additional Detail
Mark Webster, Intersil

22. FEC Decoder Detail Error pattern is easily output from FEC decoder
July 2002
FEC Decoder Detail
Error pattern is easily output from FEC decoder
Error Pattern
d(D)+g(D)E(D)
Mark Webster, Intersil

23. July 2002
Using an FEC Codec Core
QUESTION: I have a Reed-Solomon IP core where I do not have
access to the error pattern. How can I generate the error pattern?
CONVENTIONAL FEC CORE
Receive Bits
Corrected Bits
FEC DECODER
CORE
GENERATING ERROR PATTERN
Receive Bits
Corrected Bits
FEC DECODER
CORE - + +
Error Pattern
Mark Webster, Intersil

24. Simple Components, Low Latency, Little Buffering
July 2002
Simple Components, Low Latency, Little Buffering D4 D3 +
FIR Bit-Filter, g(D)
IIR Bit-Filter, 1/g(D) + + D4 D3
FEC DECODER
CORE
Receive Bits
Corrected Bits
Error Pattern + -
Mark Webster, Intersil

25. Recovering Bit Errors E(D): Linear Superposition
July 2002
Recovering Bit Errors E(D): Linear Superposition
In practice,
Provided by FEC decoder
1st octet is discarded to eliminate self-sync start-up errors d(D)
Bit
Errors
Self-Sync
FIR
IIR
E(D)
g(D)E(D)
E(D)
PHY
g(D)
1/g(D)
IIR state must match FIR state
IIR is not self-synchronizing
IIR state must not contain false errors
IIR has infinite false-error propagation
It is shown how to do this on next 2 pages
Mark Webster, Intersil

26. Example: Trim Error Pattern and Jam IIR State
July 2002
Example: Trim Error Pattern and Jam IIR State
Error Pattern provided by FEC Decoder …
At this point trim-off precursor.
g(D) is error-flushed with probability = 1 …
Self-Sync
FIR
IIR
Trim Input
To Start at
Zero State
Trimmed
E(D)
PHY
g(D)
1/g(D)
Jam Error Pattern
State=0
Mark Webster, Intersil

27. Trim Error Pattern and Jam IIR State to Zero
July 2002
Trim Error Pattern and Jam IIR State to Zero
8 octets in error maximum at FEC input, so 48 – 8 = 40 octets in MAC header are not in error
Min-Max separation between FEC-input error octets is 48/8 = 6 octets. Therefore, >= 5 sequential octets are not in error in any given MAC header.
Therefore, FEC-input error pattern always has a straight of 5*8 = 40 bit-zeros or longer
At the end of 40 bits of zeros at FEC input, the self-sync FIR has been flushed (state=0) with essentially probability = 1
Jam IIR to same state (state=0) and start injecting error pattern into IIR filter at this point
Only a PHY-output bit-error pattern which matches the scrambling sequence can spoof this. But, if this occurs the bit-error-rate is nearly 50%, and the octet error rate is 100%. The spoof can only occur on frames impossible to FEC decode. Spoof rate rate << 2-40
Mark Webster, Intersil

28. Example Where g(D) Flush Event is Spoofed (<< 2-40 event)
July 2002
Example Where g(D) Flush Event is Spoofed (<< 2-40 event)
Thermal bit-error-rate is 50%
Thermal octet-error-rate is 100%
(Matches scrambling pattern)
PHY Output Thermal Bit-Error-Pattern
(Provided by FEC Decoder)
FEC-Input Bit-Error-Pattern
It appears g(D) FIR
Is flushed of errors
Self-Sync
FIR
E(D)
g(D)E(D)
FEC
Decode
PHY
g(D)
But, G(d) is never flushed
Of errors
Mark Webster, Intersil

29. July 2002
Conclusion
This submission has described a technique for restoring the full performance of the e FEC in the face of a scrambler mismatch
The power of both dual precoding and FEC correction is used to compute mismatch
No additional overhead is used
The technique is simple to implement
Mark Webster, Intersil