1. Day 18: October 20, 2010 Ratioed Logic Pass Transistor Logic
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 18: October 20, 2010
Ratioed Logic
Pass Transistor Logic
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2. Today Ratioed Gates Pass Transistor Logic Correctness Performance
Power
Implications
Pass Transistor Logic
Muxes
Composition
Logic
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3. Ratioed Logic Idea Maybe only need to build one network
Build NFET pulldown
Exploit high N mobility
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4. Size for R0/2 drive?
…and Vol<0.1Vdd
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5. Compare Static CMOS Total Transistor Width Input capacitance load
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6. Power? Istatic ? Output high? Output low? Ileak Ipmos_on
Vdd/(R0/2) -- for our sample case
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7. Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon
+(1-Plow)VI’s(W/L)e-Vt/(nkT/q)
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8. How size for R0/2 drive?
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9. How size for R0/2 drive?
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10. Which Implementation is faster in ratioed logic?
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11. Illustrates
Preferred gate changes
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12. How size for R0/2 drive?
K-input nor
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13. When better than CMOS nor-k?
Better = smaller, lower input capacitance
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14. Ratioed Logic Tradeoff noise margin for
Reduced area? Capacitive load?
Dissipates static power in one mode
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15. Admin Project: Due Friday Midterm: next Wednesday
(one week from today)
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16. Pass Transistor Logic
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17. What does this do? S A B
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18. Behavior What is the equivalent logic function? S A B
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19. Size Comparison How does this compare to the static CMOS alternative?
transistor count?
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20. Delay Assume R0/2 drive 10C0 load What else need to know? 5 2 5
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21. Delay Assume R0/2 drive 10C0 load What else need to know? Cdiff
Assume Cdiff≈Cgate 5 2
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22. What’s different? What’s different about the output?
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23. Output ok?
Is the output usable?
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24. CMOS DC Transfer Function
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25. After CMOS Inverter
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26. What does this do?
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27. Cascade Functional?
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28. Voltage Drop
Voltage drop across any number of series transistors is one Vth
Think about two series transistors as one transistor of twice the length
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29. Pinch Off Day 9 When voltage drops below VT, drops out of inversion
Occurs when: VGS-VDS< VT
Conclusion:
current cannot increase with VDS once VDS> VGS-VT
current must adjust so that VDS= VGS-VT
If current dropped to zero, then would invert and conduct again…
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30. Performance? Assume R0/2 drive 10C0 load Cdiff=Cgate 5 2 5
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31. What does this do? A B
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32. Performance
R0/2 drive
10C0 load 5 2 5
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33. Performance
R0/2 drive
10C0 load
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34. Not Isolating Does not isolate downstream capacitive load
Stage delay now dependent on downstream stages
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35. Ideas There are other logic disciplines We have the tools to analyze
Ratioed Logic
Tradeoff noise margin for
Reduced area? Capacitive load?
Dissipates static power in one mode
Pass Transistor Logic
Possibly smaller
Not rail-to-rail
Cascading without buffering  slow
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