Electrical and Computer Engineering

Electrical and Computer Engineering
EEL 5764: Graduate Computer Architecture Appendix A - Pipelining Review Ann Gordon-Ross Electrical and Computer Engineering University of Florida These slides are provided by: David Patterson Electrical Engineering and Computer Sciences, University of California, Berkeley Modifications/additions have been made from the originals CS252 S05

What is Pipelining? Overlapping execution to produce faster results
Washing and drying dishes Washing and drying laundry Automobile assembly line Chipotle, Quiznos, etc Pipelining in computer architecture Multiple instructions are overlapped in execution Exploits parallelism Not visible to programmer Each stage is a pipeline “cycle” Each stage happens simultaneously so results are produced only as fast as the longest pipeline cycle Determines clock cycle time For both auto assembly and food service, could have number of people equal to number of steps and produce same results, but only if each person was a master at all steps - jack of all trades. Pipelining allows specialization thus faster execution. But if not multiple assembly lines, still pipelined execution. 2/22/2019 CS252 S05

Outline MIPS – An ISA for Pipelining 5 stage pipelining
Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts 2/22/2019

A "Typical" RISC ISA (Load/Store)
32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero) ALU instructions 3-address, reg-reg arithmetic instruction 2-address, reg-im arithmetic instruction Single address mode for load/store: base + displacement no indirection Simple branch conditions Delayed branch RISC invented to be easy to pipeline All instructions same length Load/store only instructions that access memory Simple branches 2/22/2019 CS252 S05

Example: MIPS ( MIPS) Register-Register Op Rs1 Rs2 Rd Opx
31 26 25 21 20 16 15 11 10 6 5 Op Rs1 Rs2 Rd Opx Register-Immediate 31 26 25 21 20 16 15 immediate Op Rs1 Rd Branch 31 26 25 21 20 16 15 immediate Op Rs1 Rs2/Opx Jump / Call 31 26 25 target Op 2/22/2019

Datapath vs Control (FSM+D)
Controller signals Control Points Datapath: Storage, FU, interconnect sufficient to perform the desired functions Inputs are Control Points Outputs are signals Controller: State machine to orchestrate operation on the data path Based on desired function and signals 2/22/2019 CS252 S05

Approaching an ISA Instruction Set Architecture
Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing Meaning of each instruction is described by RTL on architected registers and memory Given technology constraints assemble adequate datapath Architected storage mapped to actual storage Function units to do all the required operations Possible additional storage (eg. MAR, MBR, …) Interconnect to move information among regs and FUs Implement controller (Finite State Machine (FSM)) How to figure out pipelining? Look at the components and FU’s you need. Map instructions to RTL statements Create FSM+D 2/22/2019 CS252 S05

Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts 2/22/2019

5 Steps of MIPS Datapath Figure A.2, Page A-8
Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC MUX 4 Adder Next SEQ PC Zero? RS1 Reg File Address Memory RS2 MUX ALU Inst Memory Data L M D RD MUX MUX Basic RTL steps. No pipelining yet! 1 clock cycle does all Sign Extend Imm WB Data 2/22/2019 CS252 S05

5 Steps of MIPS Datapath Figure A.3, Page A-9
Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX IR <= mem[PC]; PC <= PC + 4 Sign Extend With pipelining. Notice addition of pipeline registers. Each stage is a clock cycle, 5 instructions at once Why was this hard in the beginning? Instructions didn’t used to be simple steps So, RISC was invented. KISS - get rid of hard instructions RISC is likely going to stick around for a long time Imm WB Data A <= Reg[IRrs]; B <= Reg[IRrt] RD RD RD rslt <= A opIRop B WB <= rslt 2/22/2019 Reg[IRrd] <= WB CS252 S05

Inst. Set Processor Controller
IR <= mem[PC]; PC <= PC + 4 Ifetch A <= Reg[IRrs]; B <= Reg[IRrt] opFetch-DCD JSR JR ST PC <= IRjaddr if bop(A,b) PC <= PC+IRim br jmp r <= A + IRim WB <= Mem[r] Reg[IRrd] <= WB LD r <= A opIRop IRim Reg[IRrd] <= WB WB <= r RI RR r <= A opIRop B Shows what happens for each instruction type. Same up until EXE phase WB <= r Reg[IRrd] <= WB 2/22/2019 CS252 S05

Visualizing Pipelining Figure A.2, Page A-8
Time (clock cycles) Reg ALU DMem Ifetch Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7 Cycle 5 I n s t r. O r d e Nice way to show pipelining Shaded shows reading/writing Shows relationship between latency and bandwidth Shows resource overlapping 2/22/2019 CS252 S05

Pipelining is not quite that easy!
Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). 2/22/2019

One Memory Port/Structural Hazards Figure A.4, Page A-14
Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 ALU I n s t r. O r d e Load Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 1 Reg ALU DMem Ifetch Instr 2 If we had a single cache….then there would be a hazard but I and D cache are separate Advantage of diagram Register file conflict but register file is multiported Memory is not usually multiported ALU Instr 3 Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 4 2/22/2019 CS252 S05

One Memory Port/Structural Hazards (Similar to Figure A.5, Page A-15)
Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 ALU I n s t r. O r d e Load Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 1 Reg ALU DMem Ifetch Instr 2 Bubble Stall Bubble to fix Stall pipeline Reg ALU DMem Ifetch Instr 3 How do you “bubble” the pipe? 2/22/2019 CS252 S05

Speed Up Equation for Pipelining
For simple RISC pipeline, CPI = 1: Easy algebra Theoretical limitation is pipeline depth For pipelined vs unpipelined, cycle time may change 2/22/2019 CS252 S05

Example: Dual-port vs. Single-port
Machine A: Dual ported memory (“Harvard Architecture”) Machine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate Ideal CPI = 1 for both Loads are 40% of instructions executed SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe) = Pipeline Depth SpeedUpB = Pipeline Depth/( x 1) x (clockunpipe/(clockunpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 Machine A is 1.33 times faster How much faster is dual ported memory? 2/22/2019 CS252 S05

Data Hazard on R1 Figure A.6, Page A-17
Time (clock cycles) IF ID/RF EX MEM WB I n s t r. O r d e add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMem Ifetch Which are hazards? Only 2 - the 2 that go back in time 2/22/2019 CS252 S05

Three Generic Data Hazards
Read After Write (RAW) InstrJ tries to read operand before InstrI writes it Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. I: add r1,r2,r3 J: sub r4,r1,r3 Good acronym = RAW Bad description = compiler nomenclature. Will get worse…. 2/22/2019 CS252 S05

Write After Read (WAR) InstrJ writes operand before InstrI reads it Called an “anti-dependence” by compiler writers. This results from reuse of the name “r1”. Can’t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5 I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Show dependency vs. hazard. Go back to slide 18 WAR is not in RISC, in other architectures 2/22/2019 CS252 S05

Write After Write (WAW) InstrJ writes operand before InstrI writes it. Called an “output dependence” by compiler writers This also results from the reuse of name “r1”. Can’t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in more complicated pipes I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Looks like stupid code Could happen when there are branch instructions, might not actually write this code 2/22/2019 CS252 S05

Forwarding to Avoid Data Hazard Figure A.7, Page A-19
Time (clock cycles) I n s t r. O r d e add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMem Ifetch Look at timing. Notice pipeline latches have results when we need them, value can be obtained directly from the latch instead of waiting until the register file has the value. This is more complicated to do but there is no stall cycles 2/22/2019 CS252 S05

HW Change for Forwarding Figure A.23, Page A-37
ID/EX EX/MEM MEM/WR NextPC mux Registers ALU Data Memory mux mux Immediate Extra hardware you need Need muxes because sometimes value will come from reg file and sometimes from pipeline registers Mux is just if statement in sw Need 2 muxes, don’t know if reg is forwarded as first or second operand Hazards are easily handled in 5 stage pipeline What circuit detects and resolves this hazard? 2/22/2019 CS252 S05

Forwarding to Avoid LW-SW Data Hazard Figure A.8, Page A-20
Time (clock cycles) I n s t r. O r d e add r1,r2,r3 lw r4, 0(r1) sw r4,12(r1) or r8,r6,r9 xor r10,r9,r11 Reg ALU DMem Ifetch Moving data in memory Have special case for LW/SW 2/22/2019 CS252 S05

Data Hazard Even with Forwarding Figure A.9, Page A-21
Time (clock cycles) Reg ALU DMem Ifetch I n s t r. O r d e lw r1, 0(r2) sub r4,r1,r6 and r6,r1,r7 or r8,r1,r9 Forwarding doesn’t always work ALU operation after a load Need to time travel 2/22/2019 CS252 S05

Data Hazard Even with Forwarding (Similar to Figure A.10, Page A-21)
Time (clock cycles) I n s t r. O r d e Reg ALU DMem Ifetch lw r1, 0(r2) Reg Ifetch ALU DMem Bubble sub r4,r1,r6 Ifetch ALU DMem Reg Bubble and r6,r1,r7 Have to stall/bubble in this RAW dependency (load use dependency) Can use no-op to bubble No trick, gotta wait for memory Bubble Ifetch Reg ALU DMem or r8,r1,r9 How is this detected? 2/22/2019 CS252 S05

Software Scheduling to Avoid Load Hazards
Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d ,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd Can we avoid the previous stall? Compilers try to avoid load-use dependencies Optimizer would try and reorder code to add an extra cycle between load and use Gets around the dependency Compiler optimizes for performance. Hardware checks for safety. 2/22/2019 CS252 S05

Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion 2/22/2019

Control Hazard on Branches Three Stage Stall
Reg ALU DMem Ifetch 10: beq r1,r3,36 14: and r2,r3,r5 18: or r6,r1,r7 22: add r8,r1,r9 36: xor r10,r1,r11 Branches suck All instructions after branch could be wrong What do you do with the 3 instructions in between? How do you do it? Where is the “commit”? 2/22/2019 CS252 S05

Branch Stall Impact If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9! Two part solution: Determine branch taken or not sooner, AND Compute taken branch address earlier MIPS branch tests if register = 0 or  0 MIPS Solution: Move Zero test to ID/RF stage Adder to calculate new PC in ID/RF stage 1 clock cycle penalty for branch versus 3 Have to wait until register read but can do comparison early 2/22/2019 CS252 S05

Pipelined MIPS Datapath Figure A.24, page A-38
Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC ID/EX EX/MEM MEM/WB MUX 4 Adder IF/ID Adder Zero? RS1 Address Reg File Memory RS2 ALU Memory Data MUX MUX Sign Extend In ID, read register, test for 0, and calculate new PC all at once Imm WB Data RD RD RD Interplay of instruction set design and cycle time. 2/22/2019 CS252 S05

Four Branch Hazard Alternatives
#1: Stall until branch direction is clear #2: Predict Branch Not Taken Execute successor instructions in sequence “Squash” instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken 53% MIPS branches taken on average But haven’t calculated branch target address in MIPS MIPS still incurs 1 cycle branch penalty Other machines: branch target known before outcome #1 is expensive 2/22/2019 CS252 S05

Four Branch Hazard Alternatives
#4: Delayed Branch Define branch to take place AFTER a following instruction branch instruction sequential successor1 sequential successor sequential successorn branch target if taken 1 slot delay allows proper decision and branch target address in 5 stage pipeline MIPS uses this Branch delay of length n Adopted by RISC 2/22/2019 CS252 S05

Scheduling Branch Delay Slots (Fig A.14)
A. From before branch B. From branch target C. From fall through add $1,$2,$3 if $2=0 then add $1,$2,$3 if $1=0 then sub $4,$5,$6 delay slot delay slot add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes if $2=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 add $1,$2,$3 if $1=0 then sub $4,$5,$6 Limitations on delayed-branch scheduling come from 1) restrictions on the instructions that can be moved/copied into the delay slot and 2) limited ability to predict at compile time whether a branch is likely to be taken or not. In B and C, the use of $1 prevents the add instruction from being moved to the delay slot In B the sub may need to be copied because it could be reached by another path. B is preferred when the branch is taken with high probability (such as loop branches A is the best choice, fills delay slot & reduces instruction count (IC) In B, the sub instruction may need to be copied, increasing IC In B and C, must be okay to execute sub when branch fails 2/22/2019 CS252 S05

Delayed Branch Compiler effectiveness for single branch delay slot:
Fills about 60% of branch delay slots About 80% of instructions executed in branch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches Growth in available transistors has made dynamic approaches relatively cheaper 2/22/2019

Evaluating Branch Alternatives
Assume 4% unconditional branch, 6% conditional branch- untaken, 10% conditional branch-taken Scheduling Branch CPI speedup v. speedup v. scheme penalty unpipelined stall Stall pipeline Predict taken Predict not taken Delayed branch Downside, pipelines get longer and there are more branch delay slots that can’t be filled. Harder for pipelining 2/22/2019 CS252 S05

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