1. CS 3503 - Chapter 4 Dr. Clincy Professor of CS TODAY’S AGENDA
Cover a section of Ch 4
Review both Exam 2 and Exam 3
Remainder of lecture 18 online
Dr. Clincy
Lecture
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2. Memory Organization
We discussed a simple example of how memory is configured in Ch 3 – we now will cover more detail of:
How memory is laid out
How memory is addressed
Envision memory as a matrix of bits – each row implemented as a register or “storage cell” – and each row being the size of a addressable Word.
Each register or storage cell (typically called memory location) has a unique address.
The memory addresses typically start at zero and progress upward
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Lecture

3. Memory Organization
Computer memory consists of a linear array of addressable storage cells that are similar to registers.
Memory can be byte-addressable, or word-addressable, where a word typically consists of two or more bytes.
Byte-addressable case: although the Word could be multiple bytes, each individual byte would have an address – with the lowest address being the “address” of the Word
Memory is constructed of RAM chips, often referred to in terms of length  width.
If the memory word size of the machine is 16 bits, then a 4M  16 RAM chip gives us 4 megabytes of 16-bit memory locations.
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Lecture

4. Memory Organization
For alignment reasons, in reading 16-bit words on a byte-addressable machine, the address should be a multiple of 2 (i.e 2 bytes)
For alignment reasons, in reading 32-bit words on a byte-addressable machine, the address should be a multiple of 4 (i.e 4 bytes)
For alignment reasons, in reading 64-bit words on a byte-addressable machine, the address should be a multiple of 4 (i.e 8 bytes).
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Lecture

5. Memory Organization
How does the computer access a memory location corresponds to a particular address?
Memory is referred to using notation: Length x Width (L x W)
We observe that 4M can be expressed as 2 2  2 20 = 2 22 words – means 4M long with each item 8 bits wide.
Provided this is byte-addressable, the memory locations will be numbered 0 through
Thus, the memory bus of this system requires at least 22 address lines.
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6. Memory Organization
Physical memory usually consists of more than one RAM chip.
A single memory module causes all accesses to memory to be sequential - only one memory access can be performed at a time
By splitting or spreading memory across multiple memory modules (or banks), access can be performed in parallel – this is called Memory interleaving
With low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest.
In high-order interleaving, the high order address bits specify the memory bank.
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Lecture

7. Memory Organization
Example: Suppose we have a memory consisting of 16 2K x 8 bit chips.
Memory is 32K = 25  210 = 215
15 bits are needed for each address.
We need 4 bits to select the chip, and 11 bits for the offset into the chip that selects the byte.
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8. Memory Organization
In high-order interleaving the high-order 4 bits select the chip.
In low-order interleaving the low-order 4 bits select the chip.
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Lecture

9. CS3501 Exam 2 & 3 Results Exam 2 Grading Scale: Exam 3 Grading Scale:
Average E2 Score = 41 (Average Grade = 75)
E2 Score SD = 22 (very large causes odd scale)
Exam 2 Grading Scale:
A-grade (3 students)
B-grade (6 students)
C-grade (19 students)
D-grade (9 students)
Average E3 Score = 49 (Average Grade = 75)
E3 Score SD = 18 (large)
Exam 3 Grading Scale:
96-78 A-grade (4 students)
77-59 B-grade (4 students)
58-40 C-grade (15 students)
39-21 D-grade (14 students)
F-grade (0 students)
In getting your grade logged, be sure and pass back the exam after we go over them
Remainder of today’s lecture online
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10. TODAY’S AGENDA Remainder of lecture 18 online
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Lecture
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11. MARIE Instruction Set Architecture
A computer’s instruction set architecture (ISA) specifies the format of its instructions and the primitive operations that the machine can perform.
The ISA is an interface between a computer’s hardware and its software.
Some ISAs include hundreds of different instructions for processing data and controlling program execution.
The MARIE ISA consists of only thirteen instructions.
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Lecture

12. MARIE ISA This is the format of a MARIE instruction:
The fundamental MARIE instructions are:
Specifies the instruction to be executed, therefore 24=16 instructions
Allows for a maximum size of memory of
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Lecture

13. LOAD Instruction
The Load instruction allows data to be moved from memory into the CPU via the MBR and the AC
All data must be first moved into the MBR and then either into the AC or ALU
The Load instruction doesn’t have to name the AC as a final destination, the AC register is implicit in the instruction
This is a bit pattern for a LOAD instruction as it would appear in the IR:
We see that the opcode is 1 and the address from which to load the data is 3.
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Lecture

14. Intro to Other Instructions
Allows data to be moved from the CPU back to memory
Typically represented as ASCII. In real-life, has to be converted if used as numeric. For MARIE, assume numeric only
Causes the current program execution to terminate
Move the data value found at address X into the MBR, then add the MBR value to the value in the AC
Move the data value found at address X into the MBR, then subtract the MBR value from the value in the AC
Allows conditional branching (ie. while loops, if statements). When the instruction is executed, the value in the AC is inspected
Allows an unconditional branch. When the instruction is executed, it causes the contents of the Program Counter (PC) to be replaced with the value of X, which is the address of the next instruction to fetch – thus skipping
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Lecture

15. SKIPCOND Instruction
As mentioned earlier, when SKIPCOND is executed, the value in the AC is examine
In MARIE’s case, address bits 10 and 11 are examined:
Bits used to specify the condition to be tested
If 00, translates to “bypass the next instruction if the AC is negative”
If 01, translates to “bypass the next instruction if the AC is equal to 0”
If 10, translates to “bypass the next instruction if the AC is greater than 0”
If 11, an error condition occurred
This is a bit pattern for a SKIPCOND instruction as it would appear in the IR:
We see that the opcode is 8 and bits 11 and 10 are 10, meaning that the next instruction will be skipped if the value in the AC is greater than zero.
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Lecture

16. Examine Some Instructions
Opcode is binary 1, for LOAD. The address where the value in located in memory is 3. Data found at address 3 is copied into the AC
Opcode is binary 3, for ADD. The address where the value in located in memory is 13. Data found at address 13 is placed in the MBR, then the MBR value is added to the value in the AC, and then the value in the AC is over-written with the sum
Opcode is binary 8, for SKIPCOND. Bits 11 and 10 are 10 indicating bypass the next instruction if the AC is greater than 0. If the AC’s value is less than or equal to zero, this instruction is ignored and the next instruction is executed. Otherwise, the PC is incremented by 1, thus skipping
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Lecture

17. MARIE Register Transfer Notation
Instead of using binary values to represent the instruction, instruction names or mnemonics used (pronounced Nee-Monics)
Binary version – called machine instructions
Mnemonics version – called assembly language instructions
An assembler’s job is to convert the assembly instructions into the machine instructions
Recall that architectures are comprised of various components like the ALU, registers, memory decoders and control units
A single machine instruction causes these components to execute tasks
Each machine instruction can consist of multiple component-level operations
Mini-instructions are being executed. These mini-instructions are called microoperations
The exact sequence of microoperations that are carried out by an instruction can be specified using register transfer language (RTL) or register transfer notation (RTN).
In the MARIE RTL, we use the notation M[X] to indicate the actual data value stored in memory location X, and  to indicate the transfer of bytes to a register or memory location.
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18. MARIE LOAD RTL MAR  X MBR  M[MAR] AC  MBR
Loads the contents of memory location X into the AC.
The RTL for the LOAD instruction is:
Address X is placed into the MAR. The IR uses the bus to copy the value of X into the MAR
MAR  X
MBR  M[MAR]
AC  MBR
Data at location M[MAR] (or address X) is moved into the MBR. This operation and the operation above must be in sequence and can’t occur at the same time
Data is then placed in the AC. This operation can occur immediately after the above operation because the MBR and AC have a direct connection with one another
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19. MARIE STORE RTL MAR  X, MBR  AC M[MAR]  MBR
Stores the contents of the AC in memory location X.
The RTL for the STORE instruction is:
MAR  X, MBR  AC
M[MAR]  MBR
Address X is placed into the MAR and also the content or value in the AC is placed in the MBR
The contents of the MBR is stored at location M[MAR] (or address X)
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Lecture

20. MARIE ADD RTL MAR  X MBR  M[MAR] AC  AC + MBR
Data stored at memory location X is added to the AC.
The RTL for the ADD instruction is:
MAR  X
MBR  M[MAR]
AC  AC + MBR
Address X is placed into the MAR
Data at location M[MAR] (or address X) is moved into the MBR
Data in the MBR is added to the value in the AC and the result is stored back in the AC
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Lecture

21. MARIE SUB RTL MAR  X MBR  M[MAR] AC  AC - MBR
Data stored at memory location X is added to the AC.
The RTL for the ADD instruction is:
MAR  X
MBR  M[MAR]
AC  AC - MBR
Address X is placed into the MAR
Data at location M[MAR] (or address X) is moved into the MBR
Data in the MBR is subtracted from the value in the AC and the result is stored back in the AC
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Lecture

22. MARIE INPUT, OUTPUT, HALT RTL
AC  InREG
OutREG  AC
No Operation
Input for any input device is first placed into the InREG, then the data is transferred into the AC
OUTPUT
Contents of the AC is placed into the OutREG, and eventually sent out to an output device
HALT
No operations performed on registers – the machine simply ceases execution of the program
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23. MARIE JUMP RTL PC  X PC  IR[11-0]
Causes an unconditional branch to the given address, X.
The RTL for the JUMP instruction is:
PC  X
PC  IR[11-0]
Therefore to execute this instruction, the address X, must be loaded into the PC
Since the least significant 12 bits of the 16 bits is the address, the instruction above is really
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Lecture

24. MARIE SKIPCOND RTL If IR[11 - 10] = 00 then
Recall that SKIPCOND skips the next instruction according to the value of the AC.
Uses bits 10 and 11 to determine what comparison to perform on the AC
If the condition is true, the next instruction is skipped (PC incremented)
The RTL for the this instruction is the most complex in our instruction set:
If IR[ ] = 00 then
If AC < 0 then PC  PC + 1
else If IR[ ] = 01 then
If AC = 0 then PC  PC + 1
else If IR[ ] = 11 then
If AC > 0 then PC  PC + 1
Checking if AC is negative
Checking if AC is equal to zero
Checking if AC is positive
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25. Instruction Processing
The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program.
We first have to fetch an instruction from memory, and place it into the IR.
Once in the IR, it is decoded to determine what needs to be done next.
If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR.
With everything in place, the instruction is executed.
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Lecture

26. Instruction Processing – Flow Chart
When program is first loaded, the address of the first instruction is placed into the PC
Copy the contents of the PC to the MAR
If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR
Go to main memory and fetch the instruction found at address in the MAR, place it in the IR, then increment the PC by 1
With everything in place, the instruction is executed.
Decode the leftmost 4 bits of the IR in determining the opcode – and copy the rightmost 12 bits of the IR to the MAR
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27. Instruction Processing - Interrupts
All computers provide a way of interrupting the fetch-decode-execute cycle.
Interrupts occur when:
A user break (e.,g., Control+C) is issued
I/O is requested by the user or a program
A critical error occurs
Interrupts can be caused by hardware or software.
Software interrupts are also called traps.
Interrupt processing involves adding another step to the fetch-decode-execute cycle as shown below
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Lecture

28. Interrupt Instruction Processing
Interrupt service routines
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29. Interrupt - Instruction Processing
For general-purpose systems, it is common to disable all interrupts during the time in which an interrupt is being processed.
Typically, this is achieved by setting a bit in the flags register.
Interrupts that are ignored in this case are called maskable.
Nonmaskable interrupts are those interrupts that must be processed in order to keep the system in a stable condition.
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30. I/O - Instruction Processing
Interrupts are very useful in processing I/O.
However, interrupt-driven I/O is complicated, and is beyond the scope of our present discussion.
MARIE, being the simplest of simple systems, uses a modified form of programmed I/O.
All output is placed in an output register, OutREG, and the CPU polls the input register, InREG, until input is sensed, at which time the value is copied into the accumulator.
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Lecture

31. A Simple Program
Lets consider a program that adds two numbers together, storing the sum in memory
Both the assembly language program and data are stored in memory
Consider the simple MARIE program given below. We show a set of mnemonic instructions and data stored at addresses (hex):
Program
Data
Result
Assembly Language
Machine Language
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32. A Simple Program - Continuing
Let’s look at what happens inside the computer when our program runs.
This is the LOAD 104 instruction:
The PC is loaded with the address of the first instruction
The PC’s contents is stored in the MAR
The instruction at the address stored in the MAR is stored into the IR – initial instruction was fetched
PC is incremented
Address portion of the instruction is loaded into the MAR
Opcode portion is decoded
The data at the address stored in the MAR is stored into the MBR – operand 35 was fetched
The MBR’s contents is stored in the AC
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Lecture

33. A Simple Program - Continuing
The second instruction, ADD 105:
The PC’s contents is stored in the MAR (101 vs 100)
The instruction at the address stored in the MAR is stored into the IR – initial instruction was fetched
PC is incremented
Address portion of the instruction is loaded into the MAR
Opcode portion is decoded
The data at the address stored in the MAR is stored into the MBR – operand -23 was fetched
The MBR’s contents is added to the contents of the AC, and the results, 12, is stored in the AC
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Lecture

34. A Simple Program - Continued
The third instruction, STORE 106:
The PC’s contents is stored in the MAR (102 vs 101)
The instruction at the address stored in the MAR is stored into the IR – initial instruction was fetched
PC is incremented
Address where the result will be stored is loaded into the MAR
Opcode portion is decoded
No operand – this operation is not needed
The MBR’s contents is stored in main memory at the address located in the MAR
The AC’s contents is stored in the MBR
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Lecture