1. Instructor: Dr. Phillip Jones
CPRE 583 Reconfigurable Computing Lecture 21: Fri 11/12/2010 (Synthesis)
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Announcements/Reminders
HW3: finishing up (hope to release this evening) will be due Fri12/17 midnight.
Two lectures left
Fri 12/3: Synthesis and Map
Wed 12/8: Place and Route
Two class sessions for Project Presentations
Fri 12/10
Wed 12/15 (??)
Take home final given on Wed 12/15 due 12/17 5pm

3. Initial Project Proposal Slides (5-10 slides)
Project team list: Name, Responsibility (who is project leader)
Team size: 3-4 (5 case-by-case)
Project idea
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
High-level Plan
Break project into mile stones
Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Research papers related to you project idea

4. Projects Ideas: Relevant conferences
FPL
FPT
FCCM
FPGA
DAC
ICCAD
Reconfig
RTSS
RTAS
ISCA
Micro
Super Computing
HPCA
IPDPS

5. Initial Project Proposal Slides (5-10 slides)
Project team list: Name, Responsibility (who is project leader)
Project idea
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
High-level Plan
Break project into mile stones
Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Research papers related to you project idea

6. Weekly Project Updates
The current state of your project write up
Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section
The current state of your Final Presentation
Your Initial Project proposal presentation (Due Fri 10/22). Should make for a starting point for you Final presentation
What things are work & not working
What roadblocks are you running into

7. Projects: Target Timeline
Teams Formed and Idea: Mon 10/11
Project idea in Power Point 3-5 slides
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
Project team list: Name, Responsibility
High-level Plan/Proposal: Fri 10/22
Power Point 5-10 slides
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Related research papers (if any)

8. Projects: Target Timeline
Work on projects: 10/ /8
Weekly update reports
More information on updates will be given
Presentations: Last Wed/Fri of class
Present / Demo what is done at this point
15-20 minutes (depends on number of projects)
Final write up and Software/Hardware turned in: Day of final (TBD)

9. Project Grading Breakdown
50% Final Project Demo
30% Final Project Report
30% of your project report grade will come from your 5-6 project updates. Friday’s midnight
20% Final Project Presentation

10. What you should learn Intro to synthesis
Synthesis and Optimization of Digital Circuits
De micheli, 1994 (chapter 1)

11. Synthesis (big picture)
Synthesis & Optimization
Architectural Logic
Boolean
Function Min
Boolean
Relation Min
State Min
Scheduling
Sharing
Coloring Covering Satisfiability
Graph Theory
Boolean
Algebra

12. Views of a design Behavioral view Structural view PC = PC +1 Fetch(PC)
Decode(INST)
Add
Mult
Architectural level
RAM
control S1 S2
Logic level
DFF S3

13. Levels of Synthesis Architectural level
Translate the Architectural behavioral view of a design in to a structural (e.g. block level) view
Logic
Translate the logic behavioral view of a design into a gate level structural view
Behavioral view
Structural view
PC = PC +1
Fetch(PC)
Decode(INST)
Add
Mult
Architectural level
RAM
control S2 S1
Logic level
DFF S3

14. Levels of Synthesis Architectural level
Translate the Architectural behavioral view of a design in to a structural (e.g. block level) view
Logic
Translate the logic behavioral view of a design into a gate level structural view
ID Func. Resources
Schedule use (control)
Inter connect (data path)
Behavioral view
Structural view
PC = PC +1
Fetch(PC)
Decode(INST)
Add
Mult
Architectural level
RAM
control S2 S1
Logic level
DFF S3

15. Levels of Synthesis Architectural level
Translate the Architectural behavioral view of a design in to a structural (e.g. block level) view
Logic
Translate the logic behavioral view of a design into a gate level structural view
Behavioral view
Structural view
PC = PC +1
Fetch(PC)
Decode(INST)
Add
Mult
Architectural level
RAM
control S2 S1
Logic level
DFF S3

16. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if

17. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if *
ALU
Memory &
Steering logic
Control
Unit

18. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if *
ALU
Memory &
Steering logic
Control
Unit

19. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

20. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9
read S2 S8 S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

21. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 + S8 S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

22. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 * S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

23. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 S3 S7 * S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

24. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 S3 S7
*, + S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

25. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 S3 S7 * S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

26. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8 * S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

27. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
Control
Unit
S10 S1 S9 S2 S8
+,* S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

28. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size
clk’rise_edge
x1 <= x + dx;
u1 <= u – (3 * x * u * dx) – (3 * y * dx);
y1 <= y + u * dx;
if( x1 < a) then
ans_done <= 0;
else
ans_done <= 1
end if
x <= x1;
u <= u1;
y <= y1;
Control
Unit
S10 S1 S9 + S2 S8 S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

29. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size
clk’rise_edge
x1 <= x + dx;
u1 <= u – (3 * x * u * dx) – (3 * y * dx);
y1 <= y + u * dx;
if( x1 < a) then
ans_done <= 0;
else
ans_done <= 1
end if
x <= x1;
u <= u1;
y <= y1;
Control
Unit
S10 S1 S9
write S2 S8 S3 S7 S6 S5 S4 *
ALU
Control
Unit
Memory &
Steering logic

30. Example: Diffeq Forward Euler method
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if x <= x1; u <= u1; y <= y1;
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size
clk’rise_edge
x1 <= x + dx;
u1 <= u – (3 * x * u * dx) – (3 * y * dx);
y1 <= y + u * dx;
if( x1 < a) then
ans_done <= 0;
else
ans_done <= 1
end if
x <= x1;
u <= u1;
y <= y1;
Control
Unit
DFF
DFF
DFF
DFF *
ALU
Control
Unit
Memory &
Steering logic

31. Optimization Combinational Metrics: propagation delay, circuit size
Sequential
Cycle time
Latency
Circuit size

32. Optimization Combinational Metrics: propagation delay, circuit size
Sequential
Cycle time
Latency
Circuit size

33. Impact of Highlevel Syn on Optimaiztion
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if *
ALU
Memory &
Steering logic
Control
Unit

34. Impact of Highlevel Syn on Optimaiztion
y’’ + 3xy’ + 3y = 0, where x(0) = 0; y(0) =y; y’(0) = u, for x = 0 to a, dx step size clk’rise_edge x1 <= x + dx; u1 <= u – (3 * x * u * dx) – (3 * y * dx); y1 <= y + u * dx; if( x1 < a) then ans_done <= 0; else ans_done <= 1 end if *
ALU
Memory &
Steering logic
Control
Unit * * *
ALU
Memory &
Steering logic
Control
Unit

35. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models

36. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models

37. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
Sum of products
A’B’C’D’ + A’B’C’D +
A’B’CD’ + A’B’CD +
A’BCD’

38. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
K-map CD
Sum of products 00 01 10 11 AB
A’B’C’D’ + A’B’C’D +
A’B’CD’ + A’B’CD +
A’BCD’ 00 1 1 1 1 01 1 10 11

39. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
K-map CD
Sum of products 00 01 10 11 AB
A’B’C’D’ + A’B’C’D +
A’B’CD’ + A’B’CD +
A’BCD’ 00 1 1 1 1 01 1 10 11

40. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
K-map CD
Sum of products
Sum of products (minimized) 00 01 10 11 AB
A’B’C’D’ + A’B’C’D +
A’B’CD’ + A’B’CD +
A’BCD’ 00 1 1 1 1
A * B + A’*C*D’ 01 1 10 11

41. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
Multi-level high-level view
A’B’C’D’ + A’B’C’D ’
A = xy + xw
B = xw

42. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models
Multi-level high-level view
A’B’C’D’ + A’B’C’D ’
A = xy + xw
B = xw
(xy + xw)’ (xw)’CD + (xy + xw)’(xw)C’D’

43. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models

44. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models

45. Logic-level Synthesis and Optimization
Combinational
Two-level optimization
Multi-level optimization
Sequential
State-based models
Network models

46. Introduction to HW3

47. Introduction to HW3

48. Introduction to HW3

49. Next Lecture
MAP

50. Notes
Notes