1. ICS 252 Introduction to Computer Design
Lecture 4-Architectural Synthesis
Winter 2005
Eli Bozorgzadeh
Computer Science Department-UCI

2. ICS 252-Intro to Computer Design
References
Lecture notes by Kia Bazargan on High level Synthesis [©Bazargan]
Lecture note by Rajesh Gupta on scheduling [©Gupta]
Chapter 4 ( ) of the textbook
Winter 2005
ICS 252-Intro to Computer Design

3. Architectural Synthesis
Abstract model  data path (structural) and control unit (logic-level)
Constructing macroscopic structure of digital circuit
Data path: interconnection of hardware resources (arithmetic or logic), steering logic circuits, registers/memory arrays
Objectives:
Area, latency, clock cycle time, throughput ( for pipelined data path)
Winter 2005
ICS 252-Intro to Computer Design

4. Design specification for architectural synthesis
Resources
Functional resources
Primitive
Application-specific
Memory
Examples: registers, ROM, RAM
Interface
Internal: buses
External: I/O pads
Winter 2005
ICS 252-Intro to Computer Design

5. Design specification for architectural synthesis
Constraints
Interface constraints
Format and timing of the I/O data transfers
Implementation constraints
Area
Latency, cycle time
Winter 2005
ICS 252-Intro to Computer Design

6. Fundamental architectural synthesis problems
Input:
sequencing graph
a set of functional units
a set of constraints
Assumption:
Storage by registers
Interconnection by wires
Non-hierarchical graph with operations having bounded and known execution delay
Two tasks:
Placing operations in time and space
Determining the detailed interconnection of data path and control unit
Winter 2005
ICS 252-Intro to Computer Design

7. Temporal Domain: Scheduling
Given
Sequencing graph
Operations D={di,i=0,1,2,…,n}
Start time at each operation T={ti, i=1,2…,n}
Scheduling: task of determining the start time of each operation
Subject to
Precedence constraint by sequencing graph
Winter 2005
ICS 252-Intro to Computer Design

8. ICS 252-Intro to Computer Design
Scheduling
Latency of a scheduled graph:
Difference between the start time of source and sink
NOP 10 1 2 6 8
Time 1 * * * * + 9 11 7
Time 2 3 * * +
<
Time 3 4 -
Time 4 5 -
NOP
Winter 2005
ICS 252-Intro to Computer Design

9. Scheduling under resource constraints
NOP 1 10
Time 1 * + 2
Time 2 *
<
Time 3 3 * 6
Time 4 4 - * 7
Time 5 *
Time 6 8 * - 5 9
Time 7 +
Winter 2005
ICS 252-Intro to Computer Design

10. Spatial Domain: Binding
A resource binding is a mapping such that operation vi with type T is implemented with rth resource
One-to-one function, many-to-one functions (resource sharing), one-to-many functions (module selection)
On a scheduled graph
Winter 2005
ICS 252-Intro to Computer Design

11. Resource binding on a scheduled graph
NOP 10 1 2 6 8
Time 1 * * * * + 7 9 11
Time 2 3 * * +
<
Time 3 4 -
Time 4 5 -
NOP
Winter 2005
ICS 252-Intro to Computer Design

12. Area and performance estimation
Latency
By scheduling
Area
Resource-dominated
General circuit
Registers
Steering logics
Wiring
Control unit
Winter 2005
ICS 252-Intro to Computer Design

13. ICS 252-Intro to Computer Design
Strategies
Area/latency optimization
Cycle-time/area optimization
cycle-time/latency optimization
Winter 2005
ICS 252-Intro to Computer Design

14. ICS 252-Intro to Computer Design
Summary
Architectural synthesis
Optimization problem: determine schedule and binding
Problem reduces to computation of Pareto optimal points
We study area/latency trade-off (for given cycle-time)
Next: architectural optimization
Winter 2005
ICS 252-Intro to Computer Design