2. A 1-Bit Arithmetic Logic Unit
AND Result = a • b a
Result b

3. A 1-Bit Arithmetic Logic Unit
AND Result = a • b a
Result b
OR Result = a + b a
Result b

4. A 1-Bit Arithmetic Logic Unit
Operation a •
Result 1 + b
Multiplexor

5. Multiplexor
IN(0)
Result +
IN(1)
Operation

6. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

7. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

8. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

9. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

10. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

11. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

12. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

13. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

14. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum b
CarryOut
CI CI
a b a b
CO Sum

15. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum = + b
CarryOut
CI CI
a b a b
CO Sum

16. A 1-Bit Arithmetic Logic Unit
CarryIn a
Sum = + b
CarryOut
= ab + aCI + bCI
CI CI
a b a b
CO Sum

17. Sum = a b CI a b CI
Sum + a b CI a b CI

18. CarryOut
= ab + aCI + bCI a b CI +
CarryOut

19. A 1-Bit Arithmetic Logic Unit

20. Building a 32 bit ALU 1 Carry 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 a
Result

21. Building a 32 bit ALU 0 1 Carry 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 a
Result

22. Building a 32 bit ALU 1 0 1 Carry 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 a
Result

23. Building a 32 bit ALU 1 1 0 1 Carry 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 a
Result

24. Building a 32 bit ALU 1 1 1 0 1 Carry
Result

25. Building a 32 bit ALU 1 1 1 1 0 1 Carry
Result

26. Building a 32 bit ALU 0 1 1 1 1 0 1 Carry
Result

27. Building a 32 bit ALU 0 0 1 1 1 1 0 1 Carry
Result

28. Building a 32 bit ALU 0 0 0 1 1 1 1 0 1 Carry
Result

29. Building a 32 bit ALU 1 0 0 0 1 1 1 1 0 1 Carry
Result

30. Building a 32 bit ALU 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

31. Building a 32 bit ALU 0 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

32. Building a 32 bit ALU 0 0 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

33. Building a 32 bit ALU 1 0 0 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

34. Building a 32 bit ALU 0 1 0 0 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

35. Building a 32 bit ALU 0 1 0 0 0 1 0 0 0 1 1 1 1 0 1 Carry
Result

36. Building a 32 bit ALU

37. Building a 32 bit ALU
Gate Delays for a, b
and CarryIn ?

38. Sum = a b CI a b CI
Sum + a b CI a b CI

39. CarryOut
= ab + aCI + bCI a b CI +
CarryOut

40. Building a 32 bit ALU Gate Delays for a, b and CarryIn ?
Ripple Carry ALU

41. Building a 32 bit ALU Gate Delays for a, b and CarryIn ?
Ripple Carry ALU

42. What about subtraction (a – b) ?

43. What about subtraction (a – b) ?
Change the sign of b and add.
Two's complement approach how do we change the sign (negate)?

44. What about subtraction (a – b) ?
Change the sign of b and add.
Two's complement approach how do we change the sign (negate)?
Complement ( invert ) b and add 1.

45. What about subtraction (a – b) ? Set CarryIn (0) to 1

46. For Subtraction Binvert = 1 Carryin = 1 for ALU 0 S e t a 3 1 A L U RA L U R s u l C r y I n 2 O p i o b v f w B t C a r r y I n A L U 1 L e s s C a r r y O u t C a r r y I n A L U 2 L e s s C a r r y O u t C a r r y I n A L U 3 1 L e s s

47. Need to support the set-on-less-than instruction
slt $t1, $s0, $s1
remember: slt is an arithmetic instruction
produces a 1 if rs < rt and 0 otherwise

48. Need to support the set-on-less-than instruction
slt $t1, $s0, $s1
remember: slt is an arithmetic instruction
produces a 1 if rs < rt and 0 otherwise
use subtraction: (a-b) < 0 implies a < b
If a < b, Sign Bit Sum = 1
If a >= b, Sign Bit Sum = 0 (Assuming no overflow)

49. Need to support the set-on-less-than instruction
slt $t1, $s0, $s1
remember: slt is an arithmetic instruction
produces a 1 if rs < rt and 0 otherwise
use subtraction: (a-b) < 0 implies a < b
If a < b, Sign Bit Sum = 1
If a >= b, Sign Bit Sum = 0 (Assuming no overflow)
For slt
Result 0 = Sign Bit Sum
Result i = 0 for i = 1, 31

50. Add Less for slt operation: Less = 0 for i = 1,313 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O v e r f l o w c t i o n b .

51. For the most significant bit:3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d a .
For the most significant bit: O v e r f l o w c t i o n

52. For bit 0,
Less = Set

53. For bit 0,
Less = Set a b
a-b
Result

54. For bit 0,
Less = Set a b
a-b
Result

55. Need to support test for equality
beq $t5, $t6, Label
use subtraction: (a-b) = 0 implies a = b

56. Need to support test for equality
beq $t5, $t6, Label
use subtraction: (a-b) = 0 implies a = b
Zero = (Result31+Result Result0)
If Zero = 1, a = b
If Zero = 0, a != b for bne instruction
To branch, load Program Counter (PC) with address

57. For beq
Select Subtract
Zero = 1 for equal

58. Operation Control Lines
ALU Control Code Function
Bnegate Operation
and or
add
subtract
set on less than

59. MIPS 32 bit ALU Reg a Reg b Operation ALU CarryOut Overflow Zero
Result to Reg

60. Detecting Overflow
No overflow when adding a positive and a negative number
No overflow when signs are the same for subtraction
Overflow occurs when the value affects the sign:
overflow when adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive and get a negative
or, subtract a positive from a negative and get a positive

61. For the most significant bit:3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d a .
For the most significant bit: O v e r f l o w c t i o n

62. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
0 0 1
0 1 0
0 1 1
0 0
1 0 1
1 1 0
1 1 1

63. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
0 1 0
0 1 1
0 0
1 0 1
1 1 0
1 1 1

64. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
0 1 1
0 0
1 0 1
1 1 0
1 1 1

65. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
0 0
1 0 1
1 1 0
1 1 1

66. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
1 0 1
1 1 0
1 1 1

67. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
` 0
1 1 0
1 1 1

68. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
` 0
1 1 1

69. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
` 0

70. Overflow Detection
for Addition
For the sign bit, 31 in MIPS
a b CI Sum CO Overflow
` 0
Overflow = a b CI +a b CI
Overflow = CI CO + CI CO

72. MIPS 32 bit ALU Reg a Reg b Operation ALU CarryOut Overflow Zero
Result to Reg

73. 2 gate delays per bit 64 gate delays to Sum 31
MIPS 32 bit ALU
Reg a
Reg b
Operation
ALU
CarryOut
Overflow
Zero
Result to Reg
What about the speed?
2 gate delays per bit gate delays to Sum 31

74. 2 gate delays per bit 64 gate delays to Sum 31
MIPS 32 bit ALU
Reg a
Reg b
Operation
ALU
CarryOut
Overflow
Zero
Result to Reg
What about the speed?
2 gate delays per bit gate delays to Sum 31
Assume 1 nanosec: 64 nanosec which is Mhz

75. Signed and Unsigned Numbers
Numbers that are signed ( positive and negative) are
denoted as integers.

76. Signed and Unsigned Numbers
Numbers that are signed ( positive and negative) are
denoted as integers.
Other numbers are unsigned and are only positive
(like addresses). Called unsigned integers.

77. Signed and Unsigned Numbers
Consider the number
If signed, then it is – or - 7
If unsigned, then it is
= 57

78. Signed and Unsigned Numbers
Numbers that are signed ( positive and negative) are
denoted as integers.
Other numbers are unsigned and are only positive
(like addresses). Called unsigned integers.
MIPS Instructions:
slt $t0, $s0, $s1 # $t0 = 1 if $s0 < $s1 (signed)
sltu $t1, $s0, $s1 # $t1 = 1 if $s0 < $s1 (unsigned)
slti $t0, $s0, 100 # $t0 = 1 if $s0 < 100 (signed)
sltiu $t1, $s0, 100 # $t1 = 1 if $s0 < 100 (unsigned)

79. Detecting Overflow Size of numbers is limited by number of bits.
For 32 bits max is :
= 4,294,967,295 for unsigned
+or- ( ) = 2,127,488,147 for signed 32 31

80. Detecting Overflow
No overflow when adding a positive and a negative number
No overflow when signs are the same for subtraction
Overflow occurs when the value affects the sign:
overflow when adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive and get a negative
or, subtract a positive from a negative and get a positive

81. New Instructions for Overflow
The instructions add, addi and sub cause exceptions
on overflow.

82. New Instructions for Overflow
The instructions add, addi and sub cause exceptions
on overflow.
Generally an interrupt which forces a
procedure call. .

83. New Instructions for Overflow
The instructions add, addi and sub cause exceptions
on overflow.
Generally an interrupt which forces a
procedure call.
The instructions addu, addiu, subu ignore overflows.