1. Design of a High Performance PlanetLab Node: Line Card
John DeHart

2. Revision History 6/27/06 (JDD):
Created from Diversified Router version

3. Overview Heavy emphasis in these slides is on Phase 0
In fact we might view it as
Phase 0.0: with external GE Switch in place of Switch Blade
Phase 0.5: if we get the switch blade in time to incorporate it.
Probable hardware configuration:
1 NP Blade for LC
1 NP Blade for NPE
1 GP Blade
External GE Switch
Possible additions:
1 Switch Blade in place of external switch
1 NP Blade for a second NPE
On LC, I think we can view this as another Substrate Link Type
No Substrate Headers used internally or externally
All packets/frames are IP packets in Ethernet Frames
External
LC  GPE, GPE  LC
LC  NPE, NPE  LC
NPE  GPE, GPE  NPE
MN Internal Header still used between MPEs
Static Shared NP implementation of MRs.
Limited, predefined MR code options
Statically loaded
Different MR slices run the same code, just use different Filters in Lookup table.
Queuing is slightly different on each system (LC_Ingress, LC_Egress, NPE)
What about ARP?

4. System View … exception packets use internal port numbers slice pkt
GPE
exception packets use internal port numbers VS VS
NPE …
slice pkt
IPH
MN-H
Kernel/VNET
Switch LC
Default filter directs packet to GPE
Filter directs packet to NPE
IPH
IPH
daddr= nextNode
daddr= thisNode
IPH
IPH
daddr= nextNode
slice pkt
slice pkt
slice pkt
slice pkt
daddr= thisNode

5. System View: External Switch
PLC
GPE
Switch / 5
1Gb / 1
1Gb
Net LC R T M / 1
1Gb R T M
NPUA / 5
1Gb
Local
Host x4 / 4
1Gb
NPUB / 5
1Gb
How many GE Interfaces can we connect to external switch from GPE?
2 available on front panel
1 for LC to/from GPE and 1 for NPE to/from GPE?

6. System View: Switch Blade
PLC
GPE
Switch
Blade / 2
1Gb
Net R T M LC / 1
1Gb / 1
10Gb
NPE-1 / 1
10Gb
Local
Host x4 / 9
1Gb
How many GE Interfaces can we use to switch blade from GPE?
2 available on fabric
1 for LC to/from GPE and 1 for NPE to/from GPE?
NPE-2 / 1
10Gb

7. PlanetLab Ingress LC Input Frame
New PlanetLab Substrate Link Type:
Configured SL Type
LC is told at boot/init time that this is its one and only SL Type.
Similar to the way P2P-DC is handled.
SL Type: 0101b
Port: May be a don’t care
IP DAddr: Verifies that packet is for our node
IP Proto = UDP
Could be a UDP tunnel to a slice
UDP DPort: Indicates which slice
Default route is to the GPE
Key =
SL=0101b
Port: May be a don’t care.
IP DAddr = our node address
DstAddr (6B)
DstAddr (6B)
SrcAddr (6B)
Ethernet
Header
SrcAddr (6B)
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
ID/Flags/FragOff (4B)
TTL (1B)
TTL (1B)
Protocol = UDP (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Hdr Cksum (2B)
Dst Addr (4B)
Dst Addr (4B)
Header IP
Src Addr (4B)
Src Addr (4B)
IP Options (0-40B)
IP Options (0-40B)
Src Port (2B)
Src Port (2B)
UDP
Header
Dst Port (2B)
Dst Port (2B)
UDP length (2B)
UDP length (2B)
UDP checksum (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
UDP Payload
(MN Packet)
PAD (nB)
PAD (nB)
Ethernet
Trailer
CRC (4B)
CRC (4B)
PlanetLab IPv4 Key(0x5) (64 bits)
SL(4b)
0101
Port
(4b)
IP DAddr (32b)
IP Proto
(8b)
UDP DPort (16b)

8. PlanetLab Ingress LC Processing
Ingress Processing:
Similar to IPv4 MR Parse right now. Minimal IP Header checks/validation:
Check that version is IPv4
Check IP Header checksum
Ignore options (Leave as is and forward on)
Drop if fragmented (What if GPE bound?)
Extract
IP Protocol
IP Dst Addr
UDP Dst Port
Or whatever is in the 2B that would be the UDP Protocol if the IP Protocol were UDP
We shouldn’t have to worry about what might be in this field if the IP Protocol is not UDP
Perform Lookup
Result contains
Ethernet DAddr for destination blade
VLAN for destination slice (if needed)
No changes made to IP Header
Re-write Ethernet Header
Configured with Ethernet SAddr for LC
Total number of 8-Byte reads:
No VLAN, No IP Options: 4
No VLAN, Max IP Options: 9
VLAN, No IP Options: 5
VLAN, Max IP Options: 14
DstAddr (6B)
Ethernet
Header
DstAddr (6B)
SrcAddr (6B)
SrcAddr (6B)
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
ID/Flags/FragOff (4B)
TTL (1B)
TTL (1B)
Protocol = UDP (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Hdr Cksum (2B)
Dst Addr (4B)
Dst Addr (4B)
Header IP
Src Addr (4B)
Src Addr (4B)
IP Options (0-40B)
IP Options (0-40B)
Src Port (2B)
Src Port (2B)
UDP
Header
Dst Port (2B)
Dst Port (2B)
UDP length (2B)
UDP length (2B)
UDP checksum (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
UDP Payload
(MN Packet)
PAD (nB)
PAD (nB)
Ethernet
Trailer
CRC (4B)
CRC (4B)
Indicates fields that
need to be read
Indicates 8-Byte Boundaries
Assuming no IP Options

9. PlanetLab Ingress LC Output Frame
Ethernet Header is only thing that changes:
DAddr: MAC Address of GPE/NPE (Result)
40 bits are static
8 bits variable and stored in Result
SAddr: MAC Address of LC (static)
Type = 802.1Q (static)
VLAN = Slice VLAN (Result)
Type = IP (static)
Total number of 8-Byte Reads: 1
Need to read first part of IP header so when we do the write of last part of ethernet header we can fill out the 8-Byte Write.
Total number of 8-Byte Writes: 3
DstAddr (6B)
SrcAddr (6B)
Ethernet
Header
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
TTL (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Dst Addr (4B)
Header IP
Src Addr (4B)
IP Options (0-40B)
Src Port (2B)
UDP
Header
Dst Port (2B)
UDP length (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
PAD (nB)
Ethernet
Trailer
CRC (4B)
Indicates fields that
need to be written
Indicates 8-Byte Boundaries
Assuming no IP Options

10. PlanetLab Egress LC Input Frame
Ethernet Header addressed to LC
IP Packet should be complete and LC does not need to touch it. (Phase 0)
Should not even need to do hdr checksum
Lookup Key:
IP Dst Addr(32b)
Used to determine next hop Ethernet Dst Addr
DstAddr (6B)
SrcAddr (6B)
Ethernet
Header
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
TTL (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Dst Addr (4B)
Header IP
Src Addr (4B)
IP Options (0-40B)
Src Port (2B)
UDP
Header
Dst Port (2B)
UDP length (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
PAD (nB)
Ethernet
Trailer
CRC (4B)
Indicates fields that
need to be read
Indicates 8-Byte Boundaries
Assuming no IP Options

11. PlanetLab Egress LC Processing
Egress Processing:
Extract
IP Dst Addr
Perform Lookup
Need to generate
MAC DAddr for next hop
VLAN, maybe
Result contains
L2 Lookup Table Index
L2 Lookup Table Entry:
L2 Header Size (14B or 18B)
18 Bytes of Data
No changes made to IP Header
Re-write Ethernet Header
Configured with Ethernet SAddr for LC
Total number of 8-Byte reads: 2
DstAddr (6B)
SrcAddr (6B)
Ethernet
Header
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
TTL (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Dst Addr (4B)
Header IP
Src Addr (4B)
IP Options (0-40B)
Src Port (2B)
UDP
Header
Dst Port (2B)
UDP length (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
PAD (nB)
Ethernet
Trailer
CRC (4B)
Indicates fields that
need to be read
Indicates 8-Byte Boundaries
Assuming no IP Options

12. PlanetLab Egress LC Output Frame
Ethernet Header is only thing that changes.
Use the L2 Header Table to get:
DAddr: MAC Address of next hop (Result)
SAddr: MAC Address of LC (static)
Optional
Type = 802.1Q (static)
VLAN = Slice VLAN (Result)
Type = IP (static)
Total number of 8-Byte Reads: 1
Need to read first 6 Bytes of the IP header so when we do the write of last part of ethernet header we can fill out the 8-Byte Write.
Total number of 8-Byte Writes: 3
DstAddr (6B)
SrcAddr (6B)
Ethernet
Header
Type=802.1Q (2B)
VLAN (2B)
Type=IP (2B)
Ver/HLen/Tos/Len (4B)
ID/Flags/FragOff (4B)
TTL (1B)
Protocol = UDP (1B)
Hdr Cksum (2B)
Dst Addr (4B)
Header IP
Src Addr (4B)
IP Options (0-40B)
Src Port (2B)
UDP
Header
Dst Port (2B)
UDP length (2B)
UDP checksum (2B)
UDP Payload
(MN Packet)
PAD (nB)
Ethernet
Trailer
CRC (4B)
Indicates fields that
need to be written
Indicates 8-Byte Boundaries
Assuming no IP Options

13. Queuing Assume we are using an external GE switch IPv4 MR Queueing:
LC RTM:
5 internal ports go to switch for traffic to/from NPE(s) and GPE(s)
5 external ports
1 to Internet
4 to local hosts
NPE RTM
5 ports used by NPUA to switch
Each port is associated with 1 of the LC’s external ports
5 ports used by NPUB to switch
GPE
1 GE port to switch`
IPv4 MR Queueing:
Rate control per port

14. NPE Queuing Queueing on a per port basis
Ports split across NPUA and NPUB (Phase 0.0)
Rate control per port
Rate control will need to be dynamically adjustable so we can balance bandwidth usage across NPs and GPE
Each MR gets N queues per port
MRs choose how to use the N queues
Quantum assigned per MR for each port
MRs can choose how to split among their N queues
May or may not make sense to assign queues on a per MI basis
Quantum being split across the queues means that an MR with only one active MI may not get its “fair” share. Rx
(2 ME)
Demux
(1 ME)
Hdr
Format
(1 ME)
5-Port
QM/Schd
(1 ME)
Parse
(1 ME)
Lookup
(1-2 ME)
5-Port Tx
(1 ME)

15. NPE Queuing N 5-Port P Tx U A QM/Schd QM/Schd N P U B 5-Port Tx Port 1
...
Port 1 R T M
Port 2
5-Port Tx N P U A
Port 3
Port 4
SPI
Switch
Port 5
QM/Schd
...
Port 6 N P U B
Port 7
5-Port Tx
Port 8
Port 9
Port 10

16. LC Ingress Queuing 1 5-port QM support 5 GPEs
1 5-port QM support all NPEs in one Q/port

17. LC Egress Queuing Queueing on a per ME per port basis
Each MR gets 1 queue per port
Equal quantum assigned to each MR on each port
All get equal “fair share”

18. LC: Functional Blocks S W I T C H Phy Int Rx (2 ME) Key Extract (2 ME)
Lookup
(2 ME)
Hdr
Format
(1 ME)
QM/Schd
(2 ME)
Switch Tx
(2 ME) S W I T C H
Phy Int Tx
(2 ME)
QM/Schd
(2 ME)
Hdr
Format
(1 ME)
Lookup
(2 ME)
Key
Extract
(1 ME)
Switch Rx
(2 ME)

19. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
RBUF
Buf Handle(32b)
Eth. Frame
Len (16b)
Reserved
(12b)
Port
(4b)
Rx:
Function:
Coordinate transfer of packets from RBUF to DRAM

20. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
Buf Handle(32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(8b)
Eth Hdr
Len (8b)
Eth. Frame
Len (16b)
Reserved
(12b)
Port
(4b)
Lookup Key[63-32] (32b)
Lookup Key[ 31-0] (32b)
Key_Extract (2 Microengines):
Function:
Extracts lookup key.
Peel ARP packets off and send to XScale???
Notes:
Frame offset in buffer is a constant and does not need to be read from Buffer Descriptor
Ethernet Frame Length should be passed along chain so Hdr Format can figure out where to start writing its stuff.

21. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
Buf Handle(32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(8b)
Eth Hdr
Len (8b)
Eth Frame
Length (16b)
Reserved
(8b)
Eth Hdr
Len (8b)
Lookup Key[63-32] (32b)
VLAN (16b)
Stats Index (16b)
Lookup Key[ 31-0] (32b)
DAddr
(8b)
Port
(4b)
QID (20b)
Lookup: Notes on next page

22. LC Ingress: Functional Blocks
Lookup:
Function:
Performs Lookup and passes result on to Hdr Format.
Lookup Key (64b):
SL Type (4b): 0101b
Port (4b): May be a don’t care
IP DAddr (32b)
IP Proto (8b)
UDP DPort (16b)
Lookup Result (56b):
DAddr (8b): only 8 bits of Ethernet DAddr are variable, other 40 are static per node.
VLAN (12b)
QID (20b)
Stats Index (16b)
Port (4b):
For case with external switch it is the actual physical interface to use
For case with switch blade, it is just used to spread traffic across QM/Scheduler
Notes:
Does Lookup Key need to include Port? Seems like it should not.
Does Lookup still need Frame Length? Will it be maintaining any Byte Counters?
Result should not have to include RxMI, it is not used for anything.
Stats Index may be a Per MI stats index if designed.

23. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
Buf Handle(32b)
Buffer Handle(32b)
Eth Frame
Length (16b)
Reserved
(8b)
Eth Hdr
Len (8b)
Rsv
(4b)
Port
(4b)
Rsv
(4b)
QID(20b)
VLAN (16b)
Stats Index (16b)
DAddr
(8b)
Port
(4b)
QID (20b)
Stats Index (16b)
Frame Length (16b)
Hdr Format:
Function:
From lookup result:
re-writes just the ethernet header in DRAM to make frame ready to transmit.
Extract QID, Port, Stats Index and Frame Length to pass on to QM/Scheduler
May need to increment a counter based on Stats Index.
Notes:
Pass Size on to QM/Scheduler so it does not have to read buffer descriptor for Enqueue to update Q Length.
Offset to beginning of old Ethernet header should be constant but we don’t necessarily know how long it was so we don’t know where to put our new one.
Ethernet Hdr Len is used to determine where new header should go

24. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
Buffer Handle(32b)
Buffer Handle(24b)
Rsv
(3b)
Port
(4b) V 1
Rsv
(4b)
Port
(4b)
Rsv
(4b)
QID(20b)
V: Valid Bit
Stats Index (16b)
Frame Length (16b)
QM/Scheduler (See Sailesh’s slides for more details)
Function:
Enqueue and Dequeue from queues
Scheduling algorithm
Drop Policy
Notes:

25. LC Ingress: Functional Blocks
Phy Int Rx
Key
Extract
Lookup
Hdr
Format
QM/Schd
Switch Tx S W I T C H
Buffer Handle(24b)
Rsv
(3b)
Port
(4b) V 1
TBUF
V: Valid Bit
Switch TX:
Function:
Coordinate transfer of packets from DRAM to TBUF
Notes:

26. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
Buf Handle(32b)
RBUF
Eth. Frame
Len (16b)
Reserved
(12b)
Port
(4b)
Rx:
Function:
Coordinate transfer of packets from RBUF to DRAM
Memory Accesses:
SRAM: Write Buffer Descriptor
DRAM: Transfer from RBUF
Buffer Descriptor Accesses:
Write/Initialize: Buffer_Next, Buffer_Size, Offset, Free_List, Packet_Size
Notes:
Buffer Handle:
contains the SRAM address of the buffer descriptor.
from the SRAM address of the descriptor we can calculate the DRAM address of the buffer data.
Passing the offset of where the packet starts in memory will save the next block from having to read the buffer descriptor.
Perhaps we should just pass the actual DRAM Buffer Pointer?

27. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Key
Extract
Switch Rx S W I T C H
VLAN: Lookup Key
[31-16] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
TxMI: Lookup Key
[15-0] (32b)
Buf Handle(32b)
Eth. Frame
Len (16b)
Reserved
(12b)
Port
(4b)
Key_Extract:
Function:
Extracts lookup key based on type of frame that was received.
Memory Accesses:
DRAM:
Read VLAN and TxMI from Frame
SRAM: None
Buffer Descriptor Accesses: None
Notes:
Calculates DRAM Address based on SRAM descriptor address in buffer handle and the Offset passed to it by RX.

28. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
VLAN: Lookup Key
[31-16] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
TxMI: Lookup Key
[15-0] (32b)
VLAN: Lookup Key
[31-16] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
TxMI: Lookup Key
[15-0] (32b)
Rate Monitor:
Function:
Ensures that MR/MI’s behave according to their Rate Specs.
Does this need to be a separate function from the QM/Scheduler?
Memory Accesses: Unknown at this point
DRAM:
SRAM:
Buffer Descriptor Accesses: Unknown at this point
Notes:

29. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
Lookup Result [ ] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
Lookup Result [127-96] (32b)
Lookup Result [95-64] (32b)
Lookup Result [63-32] (32b)
Lookup Result [31-0] (32b)
VLAN: Lookup Key
[31-16] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
TxMI: Lookup Key
[15-0] (32b)
Lookup:
Function:
Performs Lookup and passes result on to Hdr Format.
Memory Accesses:
DRAM: None
SRAM:
TCAM Lookup
Write Lookup command
Read Lookup Result (1-5 words from TCAM SRAM Controller or other SRAM Controller)
Buffer Descriptor Accesses: None
Notes:
Lookup does no processing on the lookup result.
Need to decide how lookup result will be stored and retrieved.
See notes on TCAM for information about the issues involved.

30. LC Egress: Lookup Result Data Formats
MLI(16b)
Rsv (16b)
QID(20b)
Eth DA[47:16] (32b)
Rsv
(4b)
Port SL
Eth DA[15:0]
(16b)
IP DA (32b)
MLI(16b)
QID(20b)
Eth DA[47:16] (32b)
Rsv
(4b)
Port SL
Eth DA[15:0]
(16b)
P2P-DC
MLI(16b)
Rsv (16b)
QID(20b)
Rsv
(4b)
Port SL
P2P-Tunnel_IPv4 (w/o VLAN)
MA (w/o VLAN)
MLI(16b)
Rsv (16b)
QID(20b)
Eth DA[47:16] (32b)
Rsv
(4b)
Port SL
Eth DA[15:0]
(16b)
VLAN (16b)
IP DA (32b)
MLI(16b)
VLAN(16b)
QID(20b)
Rsv
(4b)
Port SL
MA (with VLAN)
MLI(16b)
Rsv (16b)
QID(20b)
Eth DA[47:16] (32b)
Rsv
(4b)
Port SL
Eth DA[15:0]
(16b)
VLAN (16b)
P2P-Tunnel_IPv4 (w/o VLAN)
MLI(16b)
ETYpe(16b)
MLI(16b)
EType (16b)
QID(20b)
Rsv
(4b)
Port SL
Rsv
(4b)
Port
(4b) SL
(4b)
QID(20b)
VLAN (16b)
Rsv (16b)
P2P-VLAN0
Legacy IPv4 (w/o VLAN)
Legacy IPv4 (with VLAN)

31. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
Buffer Handle(32b)
Lookup Result [ ] (32b)
Buf Handle(32b)
Eth Frame
Length (16b)
Reserved
(16b)
Lookup Result [127-96] (32b)
Lookup Result [95-64] (32b)
Lookup Result [63-32] (32b)
Lookup Result [31-0] (32b)
Rsv
(4b)
Port
(4b)
Rsv
(4b)
QID(20b)
Reserved (16b)
Frame Length (16b)
Hdr Format:
Function:
From lookup result:
re-writes headers in DRAM to make frame ready to transmit.
Extract QID to pass on to QM/Scheduler
Memory Accesses:
DRAM:
SRAM:
Read Descriptor and Re-Write Descriptor OR
Atomic Increment/Decrement some fields in Descriptor
Buffer Descriptor Accesses:
Update Size and Offset fields
Notes:
Pass Size on to QM/Scheduler so it does not have to read buffer descriptor for Enqueue to update Q Length.

32. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
Buffer Handle(32b)
Buffer Handle(24b)
Rsv
(3b)
Port
(4b) V 1
Rsv
(4b)
Port
(4b)
Rsv
(4b)
QID(20b)
V: Valid Bit
Reserved (16b)
Frame Length (16b)
QM/Scheduler (See Sailesh’s slides for more details)
Function:
Enqueue and Dequeue from queues
Scheduling algorithm
Drop Policy
Memory Accesses:
DRAM: None
SRAM:
Q-Array Reads and Writes
Scheduling Data Structure Reads and Writes
QLength Data Structure Reads and Writes
Dequeue: Read Buffer Descriptor to retrieve Packet Size
Buffer Descriptor Accesses: Read packet size
Notes:

33. LC Egress: Functional Blocks
Phy Int Tx
QM/Schd
Hdr
Format
Lookup
Rate
Monitor
Key
Extract
Switch Rx S W I T C H
TBUF
Buffer Handle(24b)
Rsv
(3b)
Port
(4b) V 1
V: Valid Bit
Switch TX:
Function:
Coordinate transfer of packets from DRAM to TBUF
Memory Accesses:
SRAM: Read Buffer Descriptor
DRAM: Transfer to TBUF
Buffer Descriptor Accesses:
Read Size and Offset
Notes:
Calculate DRAM address based on SRAM Descriptor address in buffer handle

34. LC: Notes on TCAM Lookups
See techX_Design_TCAM_Usage.ppt slides for notes on how the TCAM will be used by the Lookup Block

35. Extra
The next set of slides are for templates or extra information if needed

36. LC: Buffer Descriptor
Hopefully we can use the same buffer descriptor for the LC and the CRF Processing Engine.
There might be some fields that are used on one and not on the other but that’s ok (MR_ID, TxMI, VLAN not needed on LC)
PE Buffer Descriptor:
LW0: buffer_next 32 bits Next Buffer Pointer (in a chain of buffers)
LW1: offset bits Offset to start of data in bytes
LW1: BufferSize 16 bits Length of data in the current buffer in bytes
LW2: reserved bits reserved/unused
LW2: reserved bits reserved/unused
LW2: free_list bits Freelist ID
LW2: packet_size 16 bits (Total packet size across multiple buffers)
LW3: MR_ID bits Meta Router ID
LW3: TxMI bits Transmit Meta Interface
LW4: VLAN bits VLAN
LW4: reserved 16 bits reserved/unused
LW5: reserved 32 bits reserved/unused
LW6: reserved 32 bits reserved/unused
LW7: packet_next 32 bits pointer to next packet (unused in cell mode)
Leave multi-buffer fields there as a template for the dedicated blade implementation of a jumbo-frame MR.
Also reduces changes to Rx, Tx, and QM and reduces potential problems.
So, far I haven’t found anything extra that we need on LC.
VLAN
Packet_Next
MR_ID
TxMI
Free_List
Packet_Size
Buffer_Next
Offset
Buffer
Descriptor
Buffer_Size

37. Text Slide Template

38. Image Slide Template