1. SPP Version 1 Router QM Design
John DeHart

2. QM Scheduler Performance

3. QM Scheduler Performance

4. QM Scheduler Performance

5. QM Scheduler Performance

6. Notes on Schedulers and Interfaces
For V1, lets make the leap and go to having 4 QMs.
This will give us 20 Schedulers
For V2, we will hope to have 6 QMs
This will give us 30 Schedulers
A lookup result will designate a scheduler but NOT an interface
Sched(5b)
QM_ID(2b)
Upper limit of 4 QM MEs supported
If we want more we should have QM_ID(3b), PerQMSched(3b), PreSchedQID(14b)
PerQMSched(3b)
Each QM currently only supports 5 schedulers.
PerSchedQID(15b)
A scheduler (QM Dequeue) will be configured with an associated interface.
Dequeue reads its rate from SRAM periodically.
Rate is 16 bits, stored in a 32 bit SRAM word
We can use the other 16 bits to configure the associated physical interface.
Of course 16 bits is more than we need.
This will allow us to configure and re-configure the associated interface for each scheduler.
This will also allow us to configure the case where we use the Switch Blade and need all schedulers to send to interface 0.
Thus there should be nothing special that needs to be done by following blocks
SCR2NN in LC_Ingress
FlowStats in LC_Egress

7. Notes on Schedulers and Interfaces
Decoupling the scheduler and interface has implications for Header Format in each of the three projects
LCI: needs to know the Dst MAC Address for frame (i.e. what board it is going to)
NPE: needs to know what Src IP Addr to put on outgoing Tunnel Pkt.
LCE: needs to know what Src and Dst MAC to put on outgoing Ethernet Frame
For LCI and LCE the key is to provide enough schedulers so we can handle the load
For V1, the schedulers should be configured at boot time
Then we can also configure the HFs at boot time so they know which interface a scheduler is associated with.
Schedulers will not be dynamically changed from one interface to another in V1
For V2, we should move the NPE and LCE HFs to be after the QMs
We already planned to do this for the NPE, might as well do it for LCE also.
LCI gets no help from moving HF after QM
LCI remains statically configured.
All the information that the HFs will need to re-write the frame and pkt headers will have to be written to the buffer descriptor.
The schedulers in the QMs will output the interface that the frame is destined for so the HF will have that information provided to it.
Then we can be more dynamic with the schedulers.