1. IBM 90nm Test Chip Results
Preeti
06/014/2010

2. Clock-to-Data delay (0->1)
800 -> 570 (TMR = 40%)
Delay = 5.1ns – 1.9ns (pad_delay) = 3.2ns
CLOCK
Q2_LVT
Q0_RVT
Delay = 5.1ns

3. Clock-to-Data delay (1->0)
1000 -> 500 (TMR = 100%)
Delay = 7.4ns – 1.9ns (pad_delay) = 5.5ns
CLOCK
Q2_LVT
Q0_RVT
Delay = 7.4ns

4. Clock-to-Data Delays – Across Rp/Rap and TMRs

5. Measured Resistances
Write current is measured to be around 290uA

6. Sense Amp Structure

7. Current Sensing Architecture

8. Sense Amp Delays (0->1)

9. Sense Amp Delays (1->0)

10. Pad Delay Measurement Slides

11. Pad Delay Measurements - Setup
1 GHz Sampling Real Time oscilloscope used to measure pad delays
500MHz Pulse Generator
Real Time Oscilloscope
TESTOUT
REFERENCE
TESTIN

12. Reference-to-TESTOUT delay without Chip (1)
Measuring Frequency – 3.33 MHz

13. Reference-to-TESTOUT delay without Chip (2)
Delay between the reference and TESTOUT is 5.3ns
REFERENCE
TESTOUT

14. Reference-to-TESTOUT delay with Chip (1)

15. Reference-to-TESTOUT delay with Chip (2)
Delay between the reference and TESTOUT is 7.2 ns
Simulated Delay at TT corner = 1.84 ns
Measured Pad-to-Pad Delay = 7.2 – 5.3 = 1.9 ns
REFERENCE
TESTOUT