1. EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003
Professor Ronald L. Carter
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2. n-channel enhancement MOSFET in ohmic region
0< VT< VG
Channel
VS = 0
0< VD< VDS,sat
EOx,x> 0 n+
e-e- e- e- e- n+
Depl Reg
p-substrate
Acceptors
VB < 0
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3. Fully biased n- channel VT calc
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4. Fully biased p- channel VT calc
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5. I-V relation for n-MOS (ohmic reg)ID
non-physical
ID,sat
saturated
VDS,sat
VDS
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6. Universal drain characteristicID
VGS=VT+3V
9ID1
ohmic
saturated, VDS>VGS-VT
VGS=VT+2V
4ID1
VGS=VT+1V
ID1
VDS
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7. Substrate bias effect on VT (body-effect)
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8. Body effect data
Fig 9.9**
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9. Low field ohmic characteristics
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10. MOSFET circuit parameters
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11. MOSFET circuit parameters (cont)
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12. MOSFET equivalent circuit elements
Fig 10.51*
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13. MOS small-signal equivalent circuit
Fig 10.52*
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14. MOS channel- length modulation
Fig 11.5*
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15. Analysis of channel length modulation
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16. Channel length mod- ulated drain char
Fig 11.6*
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17. Associating the output conductanceID
ID,sat
VDS,sat
VDS
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18. Implanted n-channel enhance-ment MOSFET (ohmic region)
0< VT< VG
e- channel ele + implant ion
Channel
VS = 0
0< VD< VDS,sat
EOx,x> 0 n+
e-e- e- e- e- n+
Depl Reg
p-substrate
Acceptors
VB < 0
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19. Ion implantation* Range DRP Si & SiO2 Al Si3N4 Si Al & SiO2
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20. “Dotted box” approx**
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21. Calculating xi and DVT
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22. References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986
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