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Discussion D5.1 Section Sections 13-3, 13-4

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Presentation on theme: "Discussion D5.1 Section Sections 13-3, 13-4"— Presentation transcript:

1 Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4
Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4

2 Basic Logic Gates and Basic Digital Design
NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

3 NOT Gate -- Inverter X Y 1 1

4 NOT X ~X ~~X = X X ~X ~~X

5 AND Gate AND X Y Z X Z Y Z = X & Y

6 AND X && Y (C-programming) X and Y (VHDL) XY (textbook)

7 OR Gate OR X Y Z X Z Y Z = X | Y

8 OR X || Y (C-programming) X or Y (VHDL) X + Y (textbook)

9 Basic Logic Gates and Basic Digital Design
NOT, AND, and OR Gates NAND and NOR Gates Exclusive-OR (XOR) Gate Multiple-input Gates

10 NAND Gate NAND X Y Z 0 0 1 0 1 1 X 1 0 1 1 1 0 Z Y Z = ~(X & Y)
X Z Y Z = ~(X & Y) nand(Z,X,Y)

11 NAND Gate NOT-AND X Y W Z 0 0 0 1 0 1 0 1 X 1 0 0 1 1 1 1 0 W Z Y
X W Z Y W = X & Y Z = ~W = ~(X & Y)

12 NOR Gate NOR X Y Z 0 0 1 0 1 0 X 1 0 0 Z 1 1 0 Y Z = ~(X | Y)
X Z Y Z = ~(X | Y) nor(Z,X,Y)

13 NOR Gate NOT-OR X Y W Z 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 X W Z Y
X W Z Y W = X | Y Z = ~W = ~(X | Y)

14 Basic Logic Gates and Basic Digital Design
NOT, AND, and OR Gates NAND and NOR Gates Exclusive-OR (XOR) Gate Multiple-input Gates

15 Exclusive-OR Gate XOR X Y Z X Z 0 0 0 Y 0 1 1 1 0 1 1 1 0 Z = X ^ Y
0 0 0 Y 0 1 1 Z = X ^ Y xor(Z,X,Y) 1 0 1 1 1 0

16 XOR X ^ Y (Verilog) X $ Y (ABEL) Y xor(Z,X,Y) (Verilog)

17 Exclusive-NOR Gate XNOR X Y Z X Z 0 0 1 Y 0 1 0 1 0 0 1 1 1 Z = X ~^ Y
0 0 1 Y 0 1 0 Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) 1 0 0 1 1 1

18 Basic Logic Gates and Basic Digital Design
NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

19 Multiple-input Gates Z Z 1 2 Z Z 3 4

20 Multiple-input AND Gate
Z 1 Output is HIGH only if all inputs are HIGH Z 1 An open input will float HIGH

21 Multiple-input OR Gate
Z 2 Output is LOW only if all inputs are LOW Z 2

22 Multiple-input NAND Gate
Z 3 Output is LOW only if all inputs are HIGH Z 3

23 Multiple-input NOR Gate
Z 4 Output is HIGH only if all inputs are LOW Z 4

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