1. Chapter 6: Computer Arithmetic
Computing Machinery
Chapter 6: Computer Arithmetic

2. Integer Representations
= +0
= +1
= +2 :
= +2,147,483,647
= -0
= -1
= -2
= -2,147,483,647

3. Magnitudes of Binary Encoded Base Positions

4. Two's Complement Example: -34 in two's complement
1. Generate the magnitude of the value in binary
2. Invert each bit of the binary number (0 becomes 1 and 1 becomes 0), called 1's complement
3. Add one (1) to the one's complement to produce the two's complement. (Ignore any overflow.)
Example: -34 in two's complement
34/2 = 17 remainder 0 _ _ _ _ _ _ _ 0
17/2 = 8 remainder 1 _ _ _ _ _ _ 1 0
8/2 = 4 remainder 0 _ _ _ _ _ 0 1 0
4/2 = 2 remainder 0 _ _ _ _
2/2 = 1 remainder 0 _ _ _
1/2 = 0 remainder 1 _ _
0/2 = 0 remainder 0 _
0/2 = 0 remainder
<- magnitude of -34
<- one's complement
<- two's complement

5. Converting Between Binary, Octal, and Hexadecimal
binary octal hexadecimal decimal
A 10
B 11
C 12
D 13 E
F 15
4 C D F

6. Integer Addition and Subtraction

7. Finite Represenation in Two's Complement

8. IEEE Single-Precision Floating Point

9. IEEE Representation of p

10. IEEE Special Values

11. Integer Multiplication (Unsigned)

12. Integer Multiplication Hardware

13. Integer Multiplication (signed)
Booth's Recoding
Booth's recoding reduces the number of computations, which reduces the amount of hardware and time required to perform a multiplication
standard

14. Booth's Multiplication
M -M = 1101
x Q
A Q Q N
= 21

15. Integer Division with remainder rebuilding the dividend, Q
recurrence relation for bitwise
integer division

16. Integer Division (restoring)

17. Integer Division (non-restoring)
reformulating the
recurrence relation
restoring test can be done once at the end of the division

18. Booth's Integer Division

19. IEEE Floating-Point Multiplication

20. POWER2 Floating-Point Unit (FPU) Architecture
The IBM POWER2 Floating-Point Unit is a hardware implementation of arithmetic operations on IEEE format floating-point numbers.
"The FPU receives two instructions from the instruction cache unit (ICU). These two instructions go through a predecode stage where the FPU discards non-floating-point instructions.
The MAF unit performs all of the floating-point arithmetic instructions, such as the multiply-add fused operation, as well as all floating-point store operations."

21. FPU Arithmetic Unit