1. The Design Against Radiation Effects (DARE) design platform for TSMC 65nm process.
M. Kakoulin, S. Redant, G. Thys, S. Verhaegen, G. Franciscatto, B. Chehab, G. Pollissard, L. Berti
AMICSA, 2018

2. DARE65 DARE65: RAD HARD DESIGN PLATFORM High-performance,
cost-effective RH space applications
AIP
STD cells lib, Memory IP & IO lib
ADK
(Electrical, LVS, DRC, RAD checks, SETsim)
PROCESS
(TSMC 65 nm CMOS)
Sponsored by:

3. Commercial TSMC 65 nm LP process - CMN /CRN65LP
DARE65
THE DARE65 design platform: PROCESS
Deep Nwell option
RDL available for Flip-chip
MOM or MIM capacitors
Dual gate oxide process 1.2V (core)/2.5V(IO)
Multiple VT (high VT, standard VT, low VT)
9 Cu metal layers + last metal layer in AL pad
Regular MPW shuttle runs
Cost effective for low volume MLM runs

4. DARE65
THE DARE65 design platform: Operating conditions & Hardness goal
Parameter
Min
Typ
Max
Core voltage, V
1,08
1,2
1,32
IO voltage, V
2,25
2,5
2,75
Temperature, 0C
-55 25
+125
TID, krad
100
300
SEL, MeV.cm2/mg 70

5. DARE65 THE DARE65 design platform: SEU, SET CAPABILITY goal Parameter
Min
Typ
Max
High, MeV.cm2/mg 60
Medium, MeV.cm2/mg 25
Basic (non hardened), MeV.cm2/mg 1

6. 65 nm process NMOS core transistor radiation results (RVt) [1]
DARE65
THE DARE65 design platform: Mitigation METHODS
65 nm process NMOS core transistor radiation results (RVt) [1]
Threshold Drive current Leakage current
1 - Bonacini, P. Valerio, R. Avramidou, R. Ballabriga, F. Faccio, K. Kloukinas and A. Marchioro, 2012 JINST 7 P “Characterization of a commercial 65 nm CMOS technology for SLHC applications

7. DARE65 THE DARE65 design platform: Mitigation METHODS
No SEL is found at room temperature in all SRAM blocks at effective LET 60 MeVxcm2/mg [2].
The SEL occurs in “6T” block only at effective LET 60 MeVxcm2/mg and at high operating temperature [2].
Another test results shows the SEL effect in 65 nm commercial STD cells at even lower LET at high operating temperature (appr. LET 20 MeVxcm2/mg )
SEU cross-section LET dependence for SRAM blocks in 65 nm [2].
2 - Maxim S. Gorbunov, Member, IEEE, Pavel S. Dolotov, Student Member, IEEE, Andrey A. Antonov, Gennady I. Zebrev, Vladimir V. Emeliyanov, Member, IEEE, Anna B. Boruzdina, Andrey G. Petrov, and Anastasia V. Ulanova (2004, August). Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study.

8. DARE65 THE DARE65 design platform: Mitigation METHODS Factor TID
- No ELT transistors
- Limits of the minimum core and IO NMOS and PMOS transistors gate width
- 2 limitations are set: for digital designs and for analogue designs (larger W).
- Deep N-well
- Guard rings prevent leakage between N regions due to TID
SEL
- n+ and p+ guard rings connected to supply or ground voltages
- double contact in source/drain areas of transistors
SEU/SET
Device spacing – to avoid “double hits”
No Hot MOS (i.e. MOS where the bulk is not connected to GND or VDD).
Drive Strength Hardening – especially to create SET hardened standard cells.
SET filters
DICE FF
Bit alignment in SRAM blocks – to avoid MBU

9. DARE65 IMEC ADK Customer analogue IP design
THE DARE65 design platform: DARE65T_ADK – Design kit
IMEC ADK
Customer analogue IP design
Schematic RH rules checks
(script)
Layout RH rules checks
(Calibre)
SET simulation environment
(Striker & prober)

10. DARE65 THE DARE65 design platform: DARE65T_CORE - STD CELL Library
multi-VT (HVt, SVt, LVt) support
digital/analogue-on-top & design flow support
12 track library – 0,2 um pitch
SET & SEU hardened cells for clock & reset tree
SET hardened combinational cells
SEU hardened flipflops and latch (DICE)
totally 102 cells
raw gate density is 344 kGates/mm2
TSMC 9T SC library comparable performance
Type N
Non-SET hardened combinational cells 52
SET hardened combinational cells - 25 MeV... 7
SET hardened combinational cells - 40 MeV...
SET hardened combinational cells - 60 MeV...
Non-SET hardened sequential cells 9
SEU hardened sequential cells 2) 5
ANTENNA cells 1
TIEH and TIEL 2
Non-SEU hardened clock gating cells
SEU hardened clock gating cells 3
Filler cells 8

11. DARE65 THE DARE65 design platform: DARE65T_CORE - STD CELL Library
DARE65T_CORE DICE and standard non-RH FF

12. DARE65 THE DARE65 design platform: DARE65T_IO – IO cell library
cold-spare feature
programmable drive strength
slew rate control
programmable pull up/down
uni / bidirectional
2 kV HBM
supports 1,8/2,5V & 3,3 V supply voltage
maximum supply voltage 3,63V
breaker cells
multi power domain support
flip-chip support

13. DARE65 THE DARE65 design platform: DARE65T_IO – SSTL IO cell library
SSTL18 cells (RX_SE, RXTX_SE, RX_DIFF, RXTX_DIFF)
1.8V ± 5% supply voltage
Defined in JESD8-15A, but visibly not updated and replaced by JESD79-2F (defines ODT, levels vs speed...), the DDR2 standard
DDR2-800 support
SSTL15 cells (RX_SE, RXTX_SE, RX_DIFF, RXTX_DIFF)
1.5V ± 5% supply voltage
Definition embedded in standard of DDR3 (JESD79-3F)
Impedance calibration support
Configurable delay line
DDR3-800 support

14. DARE65 THE DARE65 design platform: dare65t_lvds – lvds io CELL LIBRARY
DARE65T_LVDS transmitter and receiver IO cells
based on 2,5 V overdrive 3,3 transistors
2,5 and 3,3 V voltage supply
up to 400 Mbps (200 MHz)

15. DARE65 THE DARE65 design platform: DARE65T_SRAM – MEMORY
Custom cell, SEL free
SPRAM compiler
DPRAM instances
DRAM custom cell: 1,9 x 2,75 um2
2 SRAM cells solutions:
Conservative SRAM cell
With intermittent guard ring, 1,5 times smaller
The DARE65 SPRAM cell: 1,9 x 1,85 um2

16. DARE65 The DARE65 design platform: DARE65T – Analogue IP Analog IP
Main features
DARE65T_PLL
MHz output frequency
2,5-32 MHz reference frequency
Supply voltage 1,2V.
DARE65_IVREF
1,2V and 2,5 supply voltages
0,6V output reference voltage
Reference current output
Accuracy (before trimming) ± 2,5 %
DARE65_ADC
10 bit resolution
Integrated temperature sensor
10 kHz sampling rate.
DARE65_POR
TBD

17. DARE65 Test vehicle  platform validation MS capability improvement
FURTHER work
Test vehicle  platform validation
MS capability improvement
SerDes: RapidIO, SpaceFiber
DDR2/3 PHY
High-speed ADC & DAC
3. Memory capability improvement
OTP & MRAM memory