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Midterm 2 review Chapter 2 - 4.

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1 Midterm 2 review Chapter 2 - 4

2 Instruction Set Architecture
Interface between the hardware and software Easy to program with and efficient to implement Regularity, simple tradeoff, constant operands Constant size, small instruction set What operations to include? What type of operands to include ? What addressing modes to include? What memory addressing modes to include? Should be optimized for the targeted application

3 Operations Computation Control flow Add, sub, mult, div, shift, …
Branch, jump, jal, ….

4 Operands Data type: int, float, immediate … Internal storage
Stack, accumulator: old style register-memory: Smaller code size, but variable cycle per instruction and harder to encode both memory address and register in an instruction register-register Larger code size but relatively constant cycle per instruction. List on page 98

5 Memory Address Modes Register Immediate Displacement ….
A list of examples on page 104

6 Branch prediction 2 bit branch predictor Correlating branch predictor
(m,n) predictor Use last m prediction result to pick a n bit predictor Tournament predictor Branch Target Buffers

7 Explore ILP Dynamic Static Tomasulo+Branch prediction=>Speculation
More info at dynamic for optimization, but smaller window More hardware, more executable compatibility Static Bigger window but less info Simple hardware, complex compiler.

8 Example Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0
Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop

9 Speculative Dynamic Machine specification
Issue rate of 1 One broadcast per cycle for CDB branch takes 1 cycle, Load takes 1 cycle, integer alu takes 1 cycle, float add takes 2 cycle float multiply takes 3 cycle. These cycle count doesn’t include write to CDB

10 Cycle 0 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 N 2 3 4 5 6 7 8 9 Cycle 0 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Mult2 Int1 Int2 Int3 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # Busy n

11 Cycle 1 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 Y Ld f0, 0(R1) issue f0 Mem(R1) 2 N 3 4 5 6 7 8 9 Cycle 1 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Mult2 Int1 Y ld R1 #1 Int2 Int3 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #1 Busy Y n

12 Cycle 2 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 Y Ld f0, 0(R1) execute F0 Mem(R1) 2 Add.d f0 f0, f2 issue #1+F2 3 N 4 5 6 7 8 9 Cycle 2 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 Y addd f2 #1 #2 Add2 N Add3 Mult1 Mult2 Int1 ld R1 Int2 Int3 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #2 Busy Y N

13 Cycle 3 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 Y Ld f0, 0(R1) Write F0 Mem(R1) 2 Add.d f0 f0, f2 Excute #1+F2 3 S.D 0(R1), F0 issue 4 N 5 6 7 8 9 Cycle 3 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 Y addd f2 #1 #2 Add2 N Add3 Mult1 Mult2 Int1 ld R1 Int2 sd Int3 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #2 Busy Y N

14 Cycle 4 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 N Ld f0, 0(R1) commit F0 Mem(R1) 2 Y Add.d f0 f0, f2 Excute #1+F2 3 S.D 0(R1), F0 4 L.D F0, 0(R2) Issue Mem(R2) 5 6 7 8 9 Cycle 4 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 Y addd f0 f2 #2 Add2 N Add3 Mult1 Mult2 Int1 ld R1 #1 Int2 sd Int3 R2 #4 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #4 Busy Y N

15 Cycle n Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 N Ld f0, 0(R1) Commit F0 Mem(R1) 2 Add.d f0 f0, f2 #1+F2 3 S.D 0(R1), F0 4 L.D F0, 0(R2) Mem(R2) 5 Y Mult.D F0, F0, F2 Write 6 S.D 0(R2), F0 execute 7 SUBI R1, R1, 8 Execute R1 R1+8 8 SUBI R2, R2, 8 R2 R2+8 9 Bnez r2, loop Issue Cycle n Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Y Multd f0 f2 #5 Mult2 Int1 sd r2 #6 Int2 Subi R1 #7 Int3 subi #8 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #5 Busy Y N

16 Cycle n+1 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 N Ld f0, 0(R1) issue F0 Mem(R1) 2 Add.d f0 f0, f2 Commit #1+F2 3 S.D 0(R1), F0 4 L.D F0, 0(R2) Mem(R2) 5 Mult.D F0, F0, F2 commit F0*F2 6 Y S.D 0(R2), F0 execute 7 SUBI R1, R1, 8 write R1 R1+8 8 SUBI R2, R2, 8 R2 R2+8 9 Bnez r2, loop Issue Cycle n+1 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Multd f0 f2 #5 Mult2 Int1 Y sd r2 #6 Int2 Subi R1 #7 Int3 subi #8 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # Busy N

17 Cycle n+2 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 Y Ld f0, 0(R1) issue F0 Mem(R1) 2 N Add.d f0 f0, f2 Commit #1+F2 3 S.D 0(R1), F0 4 L.D F0, 0(R2) Mem(R2) 5 Mult.D F0, F0, F2 commit F0*F2 6 S.D 0(R2), F0 7 SUBI R1, R1, 8 Done write R1 R1+8 8 SUBI R2, R2, 8 write R2 R2+8 9 Bnez r2, loop Issue Cycle n+2 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Multd f0 f2 #5 Mult2 Int1 Y ld r1 #1 Int2 Subi R1 #7 Int3 subi r2 #8 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop FP register status Field F0 f2 Reorder # #1 Busy Y N

18 Cycle n+3 Reorder buffer Reservation table FP register status Field F0
Entry Busy Instruction State Destination value 1 Y Ld f0, 0(R1) issue F0 Mem(R1) 2 N Add.d f0 f0, f2 Commit #1+F2 3 S.D 0(R1), F0 4 L.D F0, 0(R2) Mem(R2) 5 Mult.D F0, F0, F2 commit F0*F2 6 S.D 0(R2), F0 7 SUBI R1, R1, 8 Execute R1 R1+8 8 SUBI R2, R2, 8 execute R2 R2+8 9 Bnez r2, loop Issue Cycle n+3 Reservation table Name Busy OP Vj Vk Qj Qk Rob des Add1 N Add2 Add3 Mult1 Multd f0 f2 #5 Mult2 Int1 Y ld r1 #1 Int2 Subi R1 #7 Int3 subi r2 #8 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R1, Loop FP register status Field F0 f2 Reorder # #1 Busy Y N

19 VLIW example Static machine specification
Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Static machine specification One delay slot between any true data flow dependency for floating point operations One branch delay slot

20 Register rename Loop: L.D F0, 0(R1) Add.D F0, F0, F2
S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F1, 0(R2) Mult.D F1, F1, F2 S.D 0(R2), F1 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop

21 Instruction reorder Loop can be unrolled to increase reorder freedom
Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F1, 0(R2) Mult.D F1, F1, F2 S.D 0(R2), F1 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Loop: L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D 0(R2), F1 SUBI R2, R2, 8 BNEZ R2, Loop SUBI R1, R1, 8 Loop can be unrolled to increase reorder freedom

22 Software pipeline Code for one iteration. 8 copies L.D F0, 0(R1)
Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D 0(R2), F1 SUBI R2, R2, 8 SUBI R1, R1, 8 BNEZ R2, Loop L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D 0(R2), F1 SUBI R2, R2, 8 SUBI R1, R1, 8 BNEZ R2, Loop L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D 0(R2), F1 SUBI R2, R2, 8 SUBI R1, R1, 8 BNEZ R2, Loop 8 copies

23 Midterm detail Take home Available online on Monday12/9 morning
Due 12/16 11:59 pm 3 questions

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