1. ECE 434 Advanced Digital System L11
Electrical and Computer Engineering University of Western Ontario

2. Outline Review: VHDL Functions, Procedures, Packages & Libraries
Networks for Arithmetic Operations
Serial Adder with Accumulator
Serial-Parallel Multiplier
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3. Review: VHDL Functions
Functions execute a sequential algorithm and return a single value to calling program
A = “ ”
General form
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4. Review: For Loops Should not be explicitly declared
Can be used inside the loop, but cannot be changed
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5. Review: VHDL Procedures
Facilitate decomposition of VHDL code into modules
Procedures can return any number of values using output parameters
General form
procedure procedure_name (formal-parameter-list) is
[declarations]
begin
Sequential-statements
end procedure_name;
procedure_name (actual-parameter-list);
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6. Review: Packages and Libraries
Provide a convenient way of referencing frequently used functions and components
Package declaration
Package body [optional]
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7. Review: VHDL Model for a 74163 Counter
74163 – 4-bit fully synchronous binary counter
Counter operations
Generate a Cout in state 15 if T=1
Cout = Q3Q2Q1Q0T
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8. Review: VHDL Model for a 74163 Counter
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9. Cascaded Counters
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10. Cascaded Counters (cont’d)
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11. Networks for Arithmetic Operations
Case Study: Serial Adder with Accumulator
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12. Networks for Arithmetic Operations
Serial Adder with Accumulator
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13. State Graphs for Control Networks
Use variable names instead of 0s and 1s
E.g., XiXj/ZpZq
if Xi and Xj inputs are 1, the outputs Zp and Zq are 1 (all other outputs are 0s)
E.g., X = X1X2X3X4, Z = Z1Z2Z3Z4
X1X4’/Z2Z3 == /
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14. Constraints on Input Labels
Assume: I – input expression => we traverse the arc when I=1
Assures that at most one input label can be 1 at any given time
Assures that at least one input label will be 1 at any given time
1 + 2: Exactly one label will be 1 => the next state will be uniquely defined for every input combination
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15. Constraints on Input Labels (cont’d)
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16. Networks for Arithmetic Operations
Case Study: Serial Parallel Multiplier
Note: we use unsigned binary numbers
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17. Block Diagram of a Binary Multiplier
Ad – add signal // adder outputs are stored into the ACC
Sh – shift signal // shift all 9 bits to right
Ld – load signal // load multiplier into the 4 lower bits of the ACC and clear the upper 5 bits
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18. Multiplication Example
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19. State Graph for Binary Multiplier
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20. Behavioral VHDL Model
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21. Behavioral VHDL Model (cont’d)
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22. Multiplier Control with Counter
Current design: control part generates the control signals (shift/add) and counts the number of steps
If the number of bits is large (e.g., 64), the control network can be divided into a counter and a shift/add control
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23. Multiplier Control with Counter (cont’d)
Counter generates a completion signal K that stops the multiplier after the proper number of shifts have been completed
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24. Multiplier Control with Counter (cont’d)
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25. Operation of a Multiplier Using Counter
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26. Array Multiplier
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27. Array Multiplier (cont’d)
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28. Multiplication of Signed Binary Numbers
How to multiply signed binary numbers?
Procedure
Complement the multiplier if negative
Complement the multiplicand if negative
Multiply two positive binary numbers
Complement the product if it should be negative
Simple but requires more hardware and time than other available methods
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29. Multiplication of Signed Binary Numbers
Four cases
Multiplicand is positive, multiplier is positive
Multiplicand is negative, multiplier is positive
Multiplicand is positive, multiplier is negative
Multiplier is negative, multiplicand is negative
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30. To Do
Read chapters 4.1, 4.2, 4.3
Do homework #3
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