1. CPRE 583 Reconfigurable Computing
Lecture 2: 8/27/2010 (VHDL Overview 1 )
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Overview
Mini Literary Survey
VHDL review 1
MP1

3. Literary Survey
Start with searching for papers from on IEEE Xplorer
Find popular cross references for each area
For each area try to identify 1 good survey papers
For each area
Identify 2-3 core Problems/issues
For each problem identify 2-3 Approaches for addressing
For each approach identify 1-2 papers that Implement the approach.

4. Literary Survey: Example Structure
Hardware Accelerated
Bioinformatics P1 P2 P3 A1 A2 A3 A1 A2 A1 A2 I1 I1 I2 I1 I1 I1 I1 I2 I1
5-10 page write up on your survey tree

5. VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage
VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
It is NOT a programming language!!!
It is a Hardware Description Language (HDL)
Conceptually VERY different form C,C++

6. Some Key Differences from C
C is inherently sequential (serial), one statement executed at a time
VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

7. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

8. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

9. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

10. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

11. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Show impact
Of changing
Order of statements

12. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

13. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

14. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2
Different

15. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

16. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

17. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4

18. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”

19. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1) +
Ans(1)
Y(1) +
X(1)
Z(1)

20. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(2)
Y(1) +
X(2)
Z(1)

21. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(4)
Y(1) +
X(2)
Z(1)

22. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1)
2ns +
Ans(1)
Y(1) +
2ns
X(1)
Z(1)
2ns

23. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(2)
Y(1) +
2ns
X(2)
Z(1)
2ns

24. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(4)
Y(1) +
2ns
X(2)
Z(1)
2ns

25. Typical Structure of a VHDL File
LIBRARY ieee;
ENTITY test_circuit IS
PORT(B,C,Y,Z,Ans);
END test_circuit;
ARCHITECTURE structure OF test_circuit IS
signal A : std_logic_vector(7 downto 0);
signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B + C;
X <= Y + Z;
Ans <= A + X;
END
Include Libraries
Define component name and
Input/output ports
Declare internal
signals,
components
Implement components
functionality

26. Process
Process provide a level serialization in VHDL (e.g. variables, clocked processes)
Help separate and add structure to VHDL design

27. Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A <= B + 1;
X <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
Sensitivity list: specify inputs to the
process. Process is updated when
a specified input changes

28. Process Example (Multiple Drivers)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
A <= B + C;
X <= Y + Z;
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A <= B + 1;
X <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
A signal can only be
Driven (written) by one
process. But can be read
by many
Compile or simulator may
give a “multiple driver” Error
or Warning message

29. Process Example (Multiple Drivers)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
A <= B + C;
X <= Y + Z;
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A1 <= B + 1;
X1 <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
Maybe A,X were suppose to be A1,X1. Cut
and paste error. Or may need to rethink
Hardware structure to remove multiple driver
issue.

30. Process Example (if-statement)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
if (B = 0) then
C <= A + B;
Z <= X + Y;
Ans1 <= A + X;
else
C <= 1;
Z <= 0;
Ans1 <= 1;
end if;
End My_process_1;
END;

31. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
circuit not clocked
A() or
C()
B()
and
Ans()
X() or
Z()
Y()

32. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
D Flip-Flop
DFF
Register
circuit with clock
A() or
C()
B()
and
Ans()
X() or
Z()
Y()
clk

33. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
circuit with clock
A() or
C()
B()
Ans()
and
X() or
Z()
Y()
clk

34. Clock Process Example 2 xor xor or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A xor B;
Z <= X or Y;
Ans <= C xor Z;
END IF;
End My_process_1;
END;
circuit with clock
A()
xor
C()
B()
Ans()
xor
X() or
Z()
Y()
clk

35. Clock Process Example 2 (Answer)
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
C <= A xor B;
Z <= X or Y;
Ans <= C xor Z;
END IF;
End My_process_1;
END;
circuit with clock
A()
xor
C()
B()
Ans()
xor
X() or
Z()
Y()
clk

36. VHDL Constructs Entity Process Signal, Variable, Constants, Integers
Array, Record
VHDL on-line tutorials:

37. Signals and Variables Signals Updated at the end of a process
Have file scope
Variables
Updated instantaneously
Have process scope
VHDL on-line tutorials:

38. std_logic, std_logic_vector
Very common data types
std_logic
Single bit value
Values: U, X, 0, 1, Z, W, H, L, -
Example: signal A : std_logic;
A <= ‘1’;
Std_logic_vector: is an array of std_logic
Example: signal A : std_logic_vector (4 downto 0);
A <= x“00Z001”
VHDL on-line tutorials:

39. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
Time step 0

40. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 U U U
Time step 0

41. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 U U
Time step 1

42. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 U
Time step 2

43. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1
Time step 3

44. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X 1
Time step 3

45. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X 1 1
Time step 3

46. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X X X 1
Time step 3

47. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor
Time step 0

48. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor U H U
Time step 0

49. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor 1 H 1
Time step 1

50. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor
Resolution(H,0) = 0 1 1
Time step 2

51. Pre-defined VHDL attributes
mysignal’event (mysignal changed value)
mysignal’high (highest value of mysignal’s type)
mysignal’low
Many other attributes

52. Singal vs Varible scope
Signal: global to file
Variable: local to process
My_process_1 : process (B,C,Y)
Begin
A <= B + C;
Z <= Y + C;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
X <= Z + 1;
Ans <= B + Y;
End My_process_2;
VHDL on-line tutorials:

53. Singal vs Varible scope
Signal: global to file
Variable: local to process
My_process_1 : process (B,C,Y)
Begin
A <= B + C;
varZ <= Y + C;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
X <= varZ + 1;
Ans <= B + Y;
End My_process_2;
Each varZ are local
to their process.
Completely independent
VHDL on-line tutorials:

54. Arrays and Records Arrays: Group signals of the same type together
Records: Group signal of different types together
VHDL on-line tutorials:

55. Array Example (Delay Shift Register)
flag_in
flag_1
flag_2
flag_3
flag_out
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_1 <= flag_in;
flag_2 <= flag_1;
flag_3 <= flag_2;
END IF;
End My_process_1;
flag_out <= flag_3
END;
VHDL on-line tutorials:

56. Array Example (Delay Shift Register)
flag_in
flag_1
flag_20
flag_out
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_1 <= flag_in;
flag_2 <= flag_1;
flag_20 <= flag_19;
END IF;
End My_process_1;
flag_out <= flag_20
END;
VHDL on-line tutorials:

57. Array Example (Delay Shift Register)
flag_in
flag_1
flag_20
flag_out
type flag_reg_array is array (DELAY-1 downto 0) of std_logic;
signal flag_reg : flag_reg_array;
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_reg(flag_reg'high downto 0) <=
flag_reg(flag_reg'high-1 downto 0) & flag_in;
END IF;
End My_process_1;
flag_out <= flag_reg(flag_reg'high);
END;

58. Array Example (Delay Shift Register)
flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in;
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1 1
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1 1
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1

59. Detailed in class design next Friday

60. Questions/Comments/Concerns

61. MP1