MODEM REGISTER VERIFICATION

MODEM REGISTER VERIFICATION

Register Name Register Address (16 – Bit) Test Case ID Purpose
Description: Read register and compare with expected value. Address: 0x600 – Expected data: 0x01 Address: 0x602 – Expected data: 0x00 Expected outcome: Time 12.19us -> Register address: 0x600 (mif_addr), Read data: 0x01 (mif_rd_data) Time 15.44us -> Register address: 0x602 (mif_addr), Read data: 0x00 (mif_rd_data) Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_DEVID (RO) 0x600, 0x602 mod_reg_mod_dev_id.c To check if device ID is updated in the register.

RSSI_VAL (RO) 0x604 mod_reg_rssi.c To check if measured RSSI value is updated in the register. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Read register and compare with expected value at BT2 side. Address: 0x604 – Expected data: 0xA9 Expected outcome: Time: us -> Register Address: 0x604 (mif_addr), Read data: 0xA9 (mif_rd_data)

Understanding: RSSI value is calculated based on AGC gain and average power. AGC gain is calculated based on LNA gain, Block 1 (Mixer) gain, Block 2 (VGA) gain. Since the received signal is attenuated in the channel model, the AGC gain adjusts the received signal to a suitable power level. Calculation: RSSI = AGC Gain – Average Power + 4 AGC Gain = LNA + B1B2= = 4F (d’79) (Signal is adjusted to the suitable power level) 2's complement of AGC gain = B1 Incoming signals average power is calculated = 0C RSSI = B1 - 0C +4 = A9

TXFUNC_CNTL_LW (RW) BT_SEL bit (Bit position – 3) 0x608 mod_reg_txfc_ctrl_bt_sel.c Test if the IUT works with the selected BT product configuration 0 - Configure BT product 0.5 (Default) 1 - Configure BT product 0.55 Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write register with value 0x0000 ( BT = 0.5) or 0x0008 (BT = 0.55).

Case 1: BT = 0.5 (iTxBTsel: 1’b0)
Contd.. Case 1: BT = 0.5 (iTxBTsel: 1’b0) Expected outcome: Time: us -> Register Address: 0x608 (mif_addr), Write data: 0x0000 (mif_wr_data) Time: us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne_1

Case 2: BT = 0.55 (iTxBTsel = 1’b1)
Contd.. Case 2: BT = 0.55 (iTxBTsel = 1’b1) Expected outcome: Time:404.03us -> Register Address: 0x608 (mif_addr), Write enable: 1’b1 (wr_en_signal), Write data: 0x0008 (mif_wr_data) Time:404.10us -> Register Address: 0x608 (mif_addr), Read data: 0x0008 (mif_rd_data) Time: us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne55_1

BT_SEL = 0.55 BT_SEL = 0.5 Understanding:
1. For BT= 0.5, the pulse shaping the symbol spreads over 2 bit period duration (Time = us for 1 packet). 2. For BT = 0.55, the symbol spread will be less than 2 bit period duration (Time = us for 1 packet). We can observe an increase of .125us for BT = 0.5 and decrease in amplitude value. Since the pulse spreads wide. For 1 bit (Bit duration=1us) the bit duration after pulse shaping will be us when BT = 0.5. For 1 bit (Bit duration=1us) the bit duration after pulse shaping will be us when BT = 0.55.

RXFUNC_CNTL_LW (RW) 1. EL_FULL_PKT_TRK (Bit position – 1) 2. EL_SLOW_TRK_ENB (Bit position – 2) 3. EL_SAMP_ADJ (Bit position – 4) 4. EL_CTRL (Bit position – 5) 5. RSSI_THRESHOLD(Bit position – 15:8) 0x61C mod_reg_el_func_ctrl.c To check early late functionality: EL_FULL_PKT_TRK - Early late tracking for full packet. EL_SLOW_TRK_ENB - Early late slow tracking for payload. EL_SAMP_ADJ - Early late sampling point adjustment. EL_CTRL - Early late sum comparison. RSSI_THRESHOLD - RSSI detection threshold for early late adjustment. Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3F0A to disable the above mentioned register bits. Write RXFUNC_CTRL register with value 0x3F3C to enable the above mentioned register bits. Write RSSI_THRESHOLD with value 0x0F and 0x3F to check if the threshold value is set correctly for Early Late adjustment.

Case 1: EL_CTRL and EL_SAMP_ADJ Disabled
Contd.. Expected outcome: 1. Time: us -> iElCtrl:1’b0, iElSampAdj:1’b0, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: 1. EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 0: When Early sum or Late sum value is greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =0: Samples will be adjusted based on Early Late threshold condition.(Matched Filter average threshold condition will not be checked).

Case 2: EL_CTRL and EL_SAMP_ADJ Enabled
Contd.. Expected outcome: 1. Time: us -> iElCtrl:1’b1, iElSampAdj:1’b1, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 1: Both Early sum and Late sum value must be greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =1: Samples will be adjusted based on Early late threshold met and matched filter average threshold.(Matched Filter average threshold condition will be checked).

Case 1: EL_SLOW_TRK_ENB Enabled
Expected outcome: Time: us -> iElSLwTrkEnb:1’b1, wElSlwTrkCntrEnb:1’b1, access_match_trig:1’b1 Understanding: EL_SLOW_TRK_ENB: Enables/disables slow tracking EL_SLOW_TRK_ENB =1 , slow tracking will be enabled and samples will be adjusted after Access address match. wSmplAdjBwdSet and wSmplAdjFwdSet are getting set after access address match.

Case 2: EL_SLOW_TRK_ENB Disabled
Expected outcome: Time: us -> iElSLwTrkEnb:1’b0, wElSlwTrkCntrEnb:1’b0, access_match_trig:1’b1 Understanding: EL_SLOW_TRK_ENB: Enables/disables slow tracking EL_SLOW_TRK_ENB =0 , slow tracking will be disabled and samples are not adjusted after Access address match. wSmplAdjBwdSet and wSmplAdjFwdSet are not getting set after access address match.

Case 1: EL_FULL_PKT_TRK Enabled
Expected outcome: Time: us -> iElTrkFullEnb:1’b0, access_match_trig:1’b1 Understanding: EL_FULL_PKT_TRK: Enables/disables Full packet tracking EL_FULL_PKT_TRK =0 , full packet tracking will be enabled and samples will be adjusted for payload. wSmplAdjBwdSet and wSmplAdjFwdSet are getting set after access address match.

Case 1: EL_FULL_PKT_TRK Disabled
Expected outcome: Time: us -> iElTrkFullEnb:1’b1, access_match_trig:1’b1 Understanding: EL_FULL_PKT_TRK: Enables/disables Full packet tracking EL_FULL_PKT_TRK =1 , full packet tracking will be disabled and samples will be adjusted till access address match (not for payload). wSmplAdjBwdSet and wSmplAdjFwdSet are not getting set after access address match.

RSSI_THRESHOLD Functionality
Expected outcome: Time: us -> iModCntrlRssiThres:7’h0F, rOperVld: 1’b0 -> 1’b1 (Continously Changing), access_match_trig:1’b0 (All packet loss) Time: us -> iModCntrlRssiThres:7’h3F, rOperVld: 1’b1, access_match_trig:1’b1(all packet received). Understanding: RSSI_THRESHOLD: RSSI value should be above the configured threshold to enable early late adjustment in the modem. If threshold value is not configured with correct value then Early late adjustment operation will not happen (Packet loss).

Contd.. Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3F40 to select the registered input data. Write RXFUNC_CTRL register with value 0x3F00 to select the input data. Register Name Register Address (16 – Bit) Test Case ID Purpose RXFUNC_CNTL_LW (RW) NORM_PH_CTRL (Bit position – 6) 0x61C mod_reg_norm_ph_ctrl.c To check the Normalizer input data selection 0 - Selects the input data 1 - Selects the registered input data

Case 1: NORM_PH_CTRL bit enabled
Expected outcome: Time: us -> iNormPhaseCtrl: 1’b1,Output signal: wNormInPhase_sel = NormInPhase_q Case 2: NORM_PH_CTRL bit disabled Time: us -> iNormPhaseCtrl: 1’b0,Output signal: wNormInPhase_sel = iNormInPhase Contd.. Understanding: NORM_PH_CTRL: Normalizer input data selection bit. NORM_PH_CTRL = 0, select the incoming input data NORM_PH_CTRL = 1, select the registered input data. To synchronize with the clock.

RXFUNC_CNTL_LW (RW) FREQ_CHCK_SUM (Bit position – 7) 0x61C mod_reg_chksum_enb.c To check enabling/disabling of frequency check sum feature 0 - Disable 1 - Enable Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3F80 to enable the frequency check sum feature. Write RXFUNC_CTRL register with value 0x3F00 to disable the frequency check sum feature.

Case 1: FREQ_CHCK_SUM bit enabled
Expected outcome: Time: us -> iFreqCheckSumEnb: 1’b0, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0000 Time: us -> iFreqCheckSumEnb: 1’b0, wFreqCheckSumFail = 1’b1,wFreqOffs:14’h0000 Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 1, compare the estimated checksum value with threshold value. wFreqCheckSumFail signal will be enabled/disabled based on the comparison. This signal is used to avoid frequency correction when there is false preamble detection. Hence FreqOffs = 0.

Case 2: FREQ_CHCK_SUM bit disabled
Expected outcome: Time: us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0007 Time: us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0000 Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 0, wFreqCheckSumFail will remain low and frequency correction will be carried out even for false preamble detection (FreqOffs = 7)

RXFUNC_CNTL_UW (RW) ADJ_CORR_VAL (Bit position – 15:10) 2. DELTA_THRES_VAL (Bit position – 9:0) 0x61E mod_reg_corr_delta_th.c To check if the configured value adjusts the correlation value from Frequency Offset Estimation module which is sent to Early Late module. To check if the configured delta threshold value adjusts the Early Late Samples. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz , Frequency Drift = 100KHz Scenario 1: Write and read RXFUNC_CTRL_UW register with value 0xFFFF (ADJ_CORR_VAL = 0x3F and DELTA_THRES_VAL=0x3FF which is the maximum value for both the bits). Scenario 2: Write and Read RXFUNC_CTRL_UW register with value 0x0001 (ADJ_CORR_VAL = 0x00 and DELTA_THRES_VAL=0x001 which is the minimum value for both the bits).

ADJ_CORR_VAL Functionality
Expected outcome: Time: us -> iAdjCorrVAl:6’h00, oPeakPosi: 6’h0A, iPeakPosiEnb:1’b1, rSampCnt:5’h10 ADJ_CORR_VAL: Correlation value will be adjusted based on the configured value. Configured value will adjust the peak position in Frequency offset estimation module. Adjusted peak position will be used in Early Late module to calculate the sample count which in turn is used to find the symbols.

DELTA_THRES_VAL Functionality
Expected outcome and understanding: iDeltaThres:10’h000, (Early – Late ) >= iDeltaThres, more samples will be adjusted since threshold value is very small. iDeltaThres:10’h3FF, (Early – Late ) >= iDeltaThres, less samples will be adjusted since threshold value is very high. No performance degradation.

MOD_CNTL_LW (RW) SM_CNTRL (Bit position – 3) 0x624 mod_reg_sm_cntrl_en.c To check the configured bit controls the sleep mode operation from modem MOD_OPER_LW (RW) SM_ENB bit (Bit position – 2) 0x628 To check the configured bit enables/disables the sleep mode operation. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_CNTL_LW register with value 0x0008 to control the sleep mode operation from modem. Write and read MOD_OPER_LW register with value 0x0004 to enable the sleep mode operation. Write and read MOD_OPER_LW register with value 0x0000 to disable the sleep mode operation.

Contd.. Expected outcome: Time = us -> wREgBankSmCntl:1’b0, wSleepEnb:1’b0, wRxClkEnb:1’b1, wRxSysClkG: 1’b1(ON) Time = us -> wREgBankSmCntl:1’b1, wSleepEnb:1’b1, wRxClkEnb:1’b0, wRxSysClkG: 1’b0(OFF) Understanding: When sleep mode operation is enabled Tx and Rx clock will be disabled and device will enter into sleep mode operation (No transmission or reception of packets).

Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0008 to enable the dynamic power. Write and read MOD_OPER_LW register with value 0x0000 to disable the dynamic power. Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) DYN_PWR_CNTRL (Bit position – 3) 0x628 mod_reg_dyn_pwr_cntrl.c To check the configured bit enables/disables the dynamic power control.

Case 1: DYN_PWR_CNTRL enabled
Contd.. Expected outcome: Time = us -> wRegBankDynPwrCntl:1’b1, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Time = us -> wRegBankDynPwrCntl:1’b1, wRxClkEnb: 1’b0, wRxSysClkG:1’b1(OFF) Case 2: DYN_PWR_CNTRL disabled Expected outcome: Time = us -> wRegBankDynPwrCntl:1’b0, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Time = us -> wRegBankDynPwrCntl:1’b0, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Understanding: When dynamic power control is enabled, it will disable the Tx and Rx clock (only when Tx and Rx operation are idle). When dynamic power control is disabled. Tx and Rx clock will be always high even when the Tx and Rx operation are idle.

MOD_OPER_LW (RW) RxClkCtrl1 (Bit position – 4) 0x628 mod_reg_rx_clk_cntrl.c To check the configured bit control the clock start stop timing for preamble search module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Preamble search module (clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0010 to disable the clock start stop timing for Preamble search module (clock will be on for entire RX)

Case 1: RxClkCtrl1 disabled
Contd.. Expected outcome: Time = us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlPreSrchClkG:1’b1(ON) Time = us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b0, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlPreSrchClkG:1’b0 (OFF)

Case 2: RxClkCtrl1 enabled
Contd.. Case 2: RxClkCtrl1 enabled Expected outcome: Time = us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlPreSrchClkG:1’b1 (ON) Time = us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlPreSrchClkG:1’b1 (ON) Understanding: Clock will be selected based on the configured bit.

MOD_OPER_LW (RW) FreqOffClkCtrl (Bit position – 5) 0x628 mod_reg_freq_off_clk_ctrl.c To check the configured bit control the clock start stop timing for frequency offset estimation module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Frequency offset estimation module (clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0020 to disable the clock start stop timing for Frequency offset estimation module (clock will be on for entire RX).

Case 1: FreqOffClkCtrl disabled
Contd.. Expected outcome: Time = us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlFreqOffEstClkG:1’b1(ON) Time = us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b0, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlFreqOffEstClkG:1’b0(OFF)

Case 2: FreqOffClkCtrl enabled
Expected outcome: Time = us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlFreqOffEstClkG:1’b1(ON) Time = us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlFreqOffEstClkG:1’b1(ON) Understanding: Clock will be selected based on the configured bit.

PreSrch2ClkCtrl (Bit position – 6)
Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) PreSrch2ClkCtrl (Bit position – 6) 0x628 mod_reg_presrch2_clk_ctrl.c To check the configured bit control the clock start stop timing for Preamble Search2 module 0 – Clk ON from RSSI Detection to Preamble Match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Preamble search2 module (clock will be on from RSSI detection to Preamble Match). Write and read MOD_OPER_LW register with value 0x0040 to disable the clock start stop timing for Preamble search2 module (clock will be on for entire RX)

Case 1: PreSrch2ClkCtrl disabled
Expected outcome: Time = us -> wRegBankPreSrch2ClkCtrl:1’b0, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, iPreMatchedLvl:1’b0, oModCntrlPreSrch2ClkG:1’b1(ON) Time = us -> wRegBankPreSrch2ClkCtrl:1’b0, rLrRx2ClkEnb: 1’b0, AgcRssiDetPosEdge:1’b0, iPreMatchedLvl:1’b1, oModCntrlPreSrch2ClkG:1’b0(OFF)

Case 2: PreSrch2ClkCtrl enabled
Expected outcome: Time = us -> wRegBankPreSrch2ClkCtrl:1’b1, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, iPreMatchedLvl:1’b0, oModCntrlPreSrch2ClkG:1’b1(ON) Time = us -> wRegBankPreSrch2ClkCtrl:1’b1, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b0, iPreMatchedLvl:1’b1, oModCntrlPreSrch2ClkG:1’b1(ON) Understanding: Clock will be selected based on the configured bit.

FRQ_DRFT_THSLD_LW (RW) FREQ_DRIFT_THRESHOLD (Bit position –13:0) 0x660 mod_reg_drft_max_limit.c Test if the configured maximum threshold value and limit value qualifies the frequency drift estimation. FRQ_DRFT_THSLD_UW (RW) FREQ_DRIFT_LIMIT_VALUE (Bit position – 13:0) 0x662 Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Drift = 100KHz. Write and read FRQ_DRFT_THSLD_LW register with maximum drift threshold value 0x0064. Write and read FRQ_DRFT_THSLD_UW register with drift limit value 0x0000 to 0x0064. Expected Outcome: Device should receive all the packets when limit value is configured with correct value (depending on the programmed value in channel model). Packet loss can be observed when limit value is not configured with correct value.

Understanding: Maximum drift threshold is the maximum drift allowed which is 100KHz.(Programmed in Channel Model) Limit value is applied whenever the drift estimation exceeds the programmed value (i.e the value in channel model). Case 1: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x64, Limit value = 0x64  All packets received Case 2: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x64  All packets received Case 3: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x30  Packet reception is degraded.

FRQ_DRFT_CFG_LW(RW) 1. FREQ_DRIFT_CONST_VAL (Bit Position – 15:2) 2. FREQ_DRIFT_CONST_EN (Bit Position – 1) 3. FREQ_DRIFT_EST_EN (Bit Position – 0) 0x664 mod_reg_freq_drift_est.c To check if the configured bit controls the Frequency Drift Estimation operation. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Drift = 100KHz. Write and read FREQ_DRIFT_EST_EN bit with 0x01 to enable the Frequency drift estimation operation. Scenario 1: 1. Write and read FREQ_DRIFT_CONST_EN bit with 0x02 to enable the constant frequency drift estimation and write FREQ_DRIFT_CONST_VAL bit with 0x064 (Depends on the channel model value) constant frequency drift value. 2. Enable ASSERT_DRIFT macro in lec_config.h. (Estimated Drift within ± 10% Tolerance) Scenario 2: 1. Write and read FREQ_DRIFT_CONST_EN bit with 0x00 to enable the actual frequency drift estimation.

Expected Outcome: When FREQ_DRIFT_CONST_EN bit is enabled, output of the Frequency Drift Estimation must be the configured constant value (FREQ_DRIFT_CONST_VAL) (Receive all the packets). When FREQ_DRIFT_CONST_EN bit is disabled, output of the Frequency Drift Estimation is the actual value estimated in the drift estimation module (Receive all the packets). The estimated frequency drift value which is not within the tolerance range will be printed on the console (Assertion should be enabled).

FRQ_DRFT_CFG_UW (RW) FREQ_DRIFT_SCALING_FACTOR_UNCODED (Bit Position – 3:0) 0x666 mod_reg_drft_fac_uncoded.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for 1M. mod_reg_drft_fac_uncoded_2M.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for 2M. FREQ_DRIFT_SCALING_FACTOR_LRC2 (Bit Position – 7:4) mod_reg_drft_fac_coded.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for LR-C2. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: 1. Write and read FRQ_DRFT_CFG_UW register with 0x9044 to select 16(2^4) as the Correlation Sum average factor to estimate the frequency drift . Scenario 2: 1. Write and read FRQ_DRFT_CFG_UW register with 0x90AA to select 1024(2^10) as the Correlation Sum average factor to estimate the frequency drift .

Expected Outcome: Expected Outcome:
Applied Frequency Drift = 100KHz, iAvgFactor = 8’h4, Estimated Frequency Drift = 14’h31.(All Packets received) Expected Outcome: Applied Frequency Drift = 100KHz, iAvgFactor = 8’hA, Estimated Frequency Drift = 14’h000.(Packet loss) Understanding: During Frequency Drift estimation, scaling of the calculated correlation sum is performed based on the configured value. 16 samples are used to calculate Correlation sum. Based on the number of samples selected for calculating correlation sum the scaling Factor must be selected.

FRQ_DRFT_CFG2_LW (RW) LRC8_BOUNDRY_ALIGN_CNTR (Bit position – 8:0) 0x668 mod_reg_boundry_align_cntr_LRC8.c To check if the configured delay counter enables the LR-C8 Frequency Drift Estimation once the 8 bit boundary align pulse is obtained. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Write and read FRQ_DRFT_CFG2_LW register with 0x130 delay counter value to enable the LRC8 frequency drift estimation.(Value 0x130 because access will match after 304us from first pulse of 8 bit boundary).

Expected Outcome: Time= us, iLrC8BndryAlignCntr:9’h130,rPreMatchedSmpCnt:13’h1300, wFreqDrftLrC8EstOn:1’b0 Understanding: Frequency Drift Estimation will start only when the count of samples from the start of preamble match is equal to the configured delay counter .

FRQ_DRFT_CFG2_LW LRC8_SAMP_CNTR_CFG (Bit Position – 10:9) 0x668 mod_reg_samp_cntr_config_LRC8.c To check if the configured value selects the number of samples to be accumulated correctly for frequency drift estimation. To check the configured value selects scaling factor. 0 – 64 samples & sampling factor = 64 1 – 128 samples & sampling factor = 128 2 – 256 samples & sampling factor = 256 3 – 512 samples & sampling factor = 512 Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: Write and read FRQ_DRFT_CFG2_LW register with 0x000 to select 64 samples to be accumulated and sampling factor as 64. Scenario 2: 1. Write and read FRQ_DRFT_CFG2_LW register with 0x600 to select 512 samples to be accumulated and sampling factor as 512.

Expected Outcome: Applied Frequency Drift = 100KHz, iLrC8SmpCntrCfg= 2’h0,wLrC8SmpCntr:9’h3F, Estimated Frequency Drift = 14’h64. Understanding: During Frequency Drift estimation, the accumulated value is used to correlation sum . Scaling is performed on the calculated correlation sum. In this scenario, 64 samples are used to calculate the correlation sum and scaling factor is also used as 64.

Expected Outcome: Applied Frequency Drift = 100KHz, iLrC8SmpCntrCfg= 2’h3,wLrC8SmpCntr:9’h1FF, Estimated Frequency Drift = 14’h64. Understanding: During Frequency Drift estimation, the accumulated value is used to correlation sum . Scaling is performed on the calculated correlation sum. In this scenario, 512 samples are used to calculate the correlation sum and scaling factor is also used as 512.

FRQ_DRFT_CFG2_UW(RW) AFC_EST_START_DLY_1M (Bit Position – 12:9) 0x66A mod_reg_afc_start_est_dly_1M.c To check if the configured delay starts the AFC estimation from preamble detection for 1M. Range 0 to 15us Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: Write and read FRQ_DRFT_CFG2_UW register with 0x0E00 to start the AFC estimation from preamble detection. Scenario 2: 1. Write and read FRQ_DRFT_CFG2_UW register with 0x000 to start the AFC estimation from preamble detection.

Expected Outcome: Time= us->iAfcDelayRef:7’h07,wAfcDelayRef1M:4’h01, rDelayCount:6’h00,wAvgEnb:1’b0, wDelayCntEnb:1’b1,wFreqEstOn:1’b1. Time= us->iAfcDelayRef:7’h07,wAfcDelayRef1M:4’h01, rDelayCount:6’h01,wAvgEnb:1’b1, wDelayCntEnb:1’b0,wFreqEstOn:1’b1 Time= us->iAfcDelayRef:7’h07,wAfcDelayRef1M:4’h01, rDelayCount:6’h00,wAvgEnb:1’b0, wDelayCntEnb:1’b0,wFreqEstOn:1’b0 Understanding: Configured delay counter will be compared with the delay count (rDelayCount). Initial offset will be provided to the estimation when the delay count is equal to the configured delay (wAfcDelayRef1M==rDelayCount)

Expected Outcome: Time= us->iAfcDelayRef:7’h0F,wAfcDelayRef1M:4’h09, rDelayCount:6’h00,wAvgEnb:1’b0, wDelayCntEnb:1’b1,wFreqEstOn:1’b1. Time= us->iAfcDelayRef:7’h0F,wAfcDelayRef1M:4’h09, rDelayCount:6’h09,wAvgEnb:1’b1, wDelayCntEnb:1’b0,wFreqEstOn:1’b1 Time= us->iAfcDelayRef:7’h0F,wAfcDelayRef1M:4’h09, rDelayCount:6’h00,wAvgEnb:1’b0, wDelayCntEnb:1’b0,wFreqEstOn:1’b0 Understanding: Configured delay counter will be compared with the delay count (rDelayCount). Initial offset will be provided to the estimation when the delay count is equal to the configured delay (wAfcDelayRef1M==rDelayCount)

FRQ_DRFT_CFG2_UW(RW) AFC_EST_START_DLY_2M (Bit Position – 15:13) 0x66A mod_reg_afc_start_est_dly_2M.c To check if the configured delay starts the AFC estimation from preamble detection for 2M. Range 0 to 7us Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: Write and read FRQ_DRFT_CFG2_UW register with 0xE000 to start the AFC estimation from preamble detection. Scenario 2: 1. Write and read FRQ_DRFT_CFG2_UW register with 0x8000 to start the AFC estimation from preamble detection.

AFC_CNTRL_EXTND_LW (RW) 1. FREQ_OFFSET_CONST_VAL (Bit Position – 15:2) 2. FREQ_OFFSET_MID_EST_EN (Bit Position – 1) 3. FREQ_OFFSET_CONST_EN (Bit Position – 0) 0x64C mod_reg_freq_offset_est.c To check if the configured bit controls the Frequency Offset Estimation operation. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: 1. Write and read FREQ_OFFSET_CONST_EN bit with 0x01 to enable the constant frequency offset estimation and write FREQ_OFFSET_CONST_VAL bit with 0x12C (Depends on the channel model value) constant frequency offset value. 2. Enable ASSERT_OFFSET macro in lec_config.h. (Estimated Offset within ± 10% Tolerance) Scenario 2: 1. Write and read FREQ_OFFSET_MID_EST_EN bit with 0x01 to enable the mid frequency offset estimation. Scenario 3: 1. Write and Read the AFC_CNTRL_EXTND_LW register with 0x0000 to enable the actual frequency offset estimation.

Expected Outcome: When FREQ_OFFSET_CONST_EN bit is enabled, output of the Frequency Offset Estimation must be the configured constant value (FREQ_OFFSET_CONST_VAL) (Receive all the packets). When FREQ_OFFSET_MID_EST_EN bit is enabled, output of the Frequency offset Estimation is based on the mid value frequency offset estimation(Receive all the packets). When FREQ_OFFSET_CONST_EN and FREQ_OFFSET_MID_EST_EN are disabled, output of the frequency estimation is the actual frequency offset value estimated in the Frequency offset estimation module (Receive all the packets). The estimated frequency offset value which is not within the tolerance range will be printed on the console (Assertion should be enabled).

TXIFMD_CNTL_UW (RW) MOD_INDEX_PHASE_VAL [10:0] 0x60E mod_reg_mod_index.c To check the transmit operation for 1M with respect to the configured modulation index value. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write and read TXIFMD_CNTL_UW register with value 0x00E6 for modulation index = 0.45 (The index value is configured based on the calculation MOD_INX_PHASE_VAL[10:0]/512). Write and read TXIFMD_CNTL_UW register with value 0x0100 for modulation index = 0.5 (The index value is configured based on the calculation MOD_INX_PHASE_VAL[10:0]/512).

Expected Outcome: Time= us, iModCntrlModIndex = 11’h0E6, oModIndValue = 161 Time= us, iModCntrlModIndex = 11’h100, oModIndValue = 180 Understanding: The GFSK data out is the saturated output of product of convolution output and the modulation value. Hence the modulation value affects the amplitude of the GFSK data out signal.

MOD_OPER_UW (RW) MOD_INDEX_PHASE_VAL2 [10:0] 0x62A mod_reg_mod_index2.c To check the transmit operation for 2M with respect to the configured modulation index value. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write and read MOD_OPER_UW register with value 0x0200 for modulation index = 0.5 (The index value is configured based on the calculation MOD_INX_PHASE_VAL2[10:0]/512). Write and read MOD_OPER_UW register with value 0x01CC for modulation index = 0.45 (The index value is configured based on the calculation MOD_INX_PHASE_VAL2[10:0]/512).

Expected Outcome: Time= us, iModCntrlModIndex2 = 11’h200, oModIndValue = 118 Time= us, iModCntrlModIndex2 = 11’h1CC, oModIndValue = 106 Understanding: The GFSK data out is the saturated output of product of convolution output and the modulation value. Hence the modulation value affects the amplitude of the GFSK data out signal.

AFC_CNTRL_EXTND_UW(RW) AFC_RETRY_WAIT_OFFST_1M (Bit Position – 5:1) AFC_RTRY_ENB (Bit Position – 0) 0x64E mod_reg_afc_retry_offset_1M.c To check if the wait delay offset value enables the AFC retry functionality when Access match address is not received for 1M PHY. Programmable value range 0 to 31 Programmable delay range 0 to 62us Offset delay programmed = (Delay value programmed * 2)us Description: Set attenuation value = -94 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Write and read AFC_CNTRL_EXTND_UW register with 0x29 (AFC_RTRY_ENB = 1 and AFC_RETRY_WAIT_OFFST_1M=0x14) to enable the AFC retry functionality for 1M PHY.

Expected Outcome: Time= us->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h014, rAfcFalseDet:1’b0, wRxEnb:1’b1, iAccessAddressTimeOut:1’b1 Time= us ->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h014, rAfcFalseDet:1’b1, wRxEnb:1’b0 , iAccessAddressTimeOut:1’b0 Time= us ->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h014, rAfcFalseDet:1’b0, wRxEnb:1’b1 , iAccessAddressTimeOut:1’b0 Understanding: Configured Offset value will retry the AFC estimation when Access address is not matched.

AFC_CNTRL_EXTND_UW (RW) AFC_RETRY_WAIT_OFFST_2M (Bit Position – 10:6) AFC_RTRY_ENB (Bit Position – 0) 0x64E mod_reg_afc_retry_offset_2M.c To check if the wait delay offset value enables the AFC retry functionality when Access match address is not received for 2M PHY. Programmable value range 0 to 31 Programmable delay range 0 to 31us Offset delay programmed = (Delay value programmed * 2)us Description: Set attenuation value = -94 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Write and read AFC_CNTRL_EXTND_UW register with 0x501 (AFC_RTRY_ENB = 1 and AFC_RETRY_WAIT_OFFST_2M=0x14) to enable the AFC retry functionality for 2M PHY.

Expected Outcome: Time= us->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h280, rAfcFalseDet:1’b0, wRxEnb:1’b1, iAccessAddressTimeOut:1’b1 Time= us ->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h280, rAfcFalseDet:1’b1, wRxEnb:1’b0 , iAccessAddressTimeOut:1’b0 Time= us ->iAfcRetryEnb:1’b1, iAfcRetryWaitDly:15’h280, rAfcFalseDet:1’b0, wRxEnb:1’b1 , iAccessAddressTimeOut:1’b0 Understanding: Configured Offset value will retry the AFC estimation when Access address is not matched.

Register Address (16 – Bit) Test Case ID Purpose Register Name
FREQ_OFFSET_DRIFT_LW (RO) I_FREQ_OFFSET (Bit Position – 13:0) 0x650 mod_reg_freq_offset_drift.c To check if estimated frequency offset is updated in the register. FREQ_OFFSET_DRIFT_UW (RO) I_FREQ_DRIFT 0x652 To check if estimated frequency drift is updated in the register. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Read FREQ_OFFSET_DRIFT_LW register value and compare with expected value (expected value 0x12C ). Read FREQ_OFFSET_DRIFT_UW register value and compare with expected value (expected value 0x64).

Expected outcome: 1. Time us -> Register address: 0x650 (mif_addr), Read data: 16’h012C (mif_rd_data), oFreqOff:14’h12C (Estimated Frequency offset). Expected outcome: 1. Time us -> Register address: 0x652 (mif_addr), Read data: 16’h064 (mif_rd_data), oDrftVal:14’h64(Estimated FrequencyDrift).

PHDISC_DIST_LW (RW) PH_DISC_DIST_1M (Bit Position – 3:0) 0x644 mod_reg_Phase_disc_dist.c To check if the configured value (1,2,4,8) selects correct phase discriminator distance (32,64,128,256) for 1M. Phase Index value is also selected based on the configured value. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Scenario 1: Write and read PHDISC_DIST_LW with 0x04 such that phase discriminator distance is 128. Scenario 2: Write and read PHDISC_DIST_LW with 0x08 such that phase discriminator distance is 256.

Expected outcome: Time us -> iPhDiscDistance:8’h04, wPhDiscDistance1M:4’h4, r1MphDiffAbsMax:10’h7F(127), wPhDiscDiffAbs:10’h28, wPhDiscDiffCap:10’h28 Time us -> iPhDiscDistance:8’h04, wPhDiscDistance1M:4’h4, r1MphDiffAbsMax:10’h7F(127), wPhDiscDiffAbs:10’h11B, wPhDiscDiffCap:10’h7F Understanding: Configured phase discriminator distance is used to limit phase values. In this scenario, if the phase values (wPhDiscDiffAbs = 0x11B) is greater than the configured phase discriminator distance(r1MphDiffAbsMax=0x7F) then phase value will be assigned with configured value (wPhDiscDiffCap = r1MphDiffAbsMax= 0x7F).

Expected outcome: Time us -> iPhDiscDistance:8’h08, wPhDiscDistance1M:4’h8, r1MphDiffAbsMax:10’hFF(255), wPhDiscDiffAbs:10’hee, wPhDiscDiffCap:10’hee Time us -> iPhDiscDistance:8’h08, wPhDiscDistance1M:4’h8, r1MphDiffAbsMax:10’hFF(255), wPhDiscDiffAbs:10’h191, wPhDiscDiffCap:10’hFF Understanding: Configured phase discriminator distance is used to limit phase values. In this scenario, if the phase values (wPhDiscDiffAbs = 0x191) is greater than the configured phase discriminator distance(r1MphDiffAbsMax=0xFF) then phase value will be assigned with configured value (wPhDiscDiffCap = r1MphDiffAbsMax= 0xFF).

Register Address (16 – Bit) Test Case ID Purpose PHDISC_DIST_LW (RW)
Register Name Register Address (16 – Bit) Test Case ID Purpose PHDISC_DIST_LW (RW) PH_DISC_DIST_2M (Bit Position – 7:4) 0x644 mod_reg_phase_disc_dist_2M.c To check if the configured value (1,2,4,8) selects correct phase discriminator distance (64,128,256,512) for 2M. Phase Index value is also selected based on the configured value. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Scenario 1: Write and read PHDISC_DIST_LW with 0x040 such that phase discriminator distance is 256. Scenario 2: Write and read PHDISC_DIST_LW with 0x010 such that phase discriminator distance is 64.

Expected outcome: Time us -> iPhDiscDistance:8’h40, wPhDiscDistance2M:4’h4, r2MphDiffAbsMax:10’hFF(255), wPhDiscDiffAbs:10’h28, wPhDiscDiffCap:10’h28 Time us -> iPhDiscDistance:8’h40, wPhDiscDistance2M:4’h4, r2MphDiffAbsMax:10’hFF(255), wPhDiscDiffAbs:10’h11B, wPhDiscDiffCap:10’hFF Understanding: Configured phase discriminator distance is used to limit phase values. In this scenario, if the phase values (wPhDiscDiffAbs = 0x11B) is greater than the configured phase discriminator distance(r2MphDiffAbsMax=0xFF) then phase value will be assigned with configured value (wPhDiscDiffCap = r2MphDiffAbsMax= 0xFF).

Expected outcome: Time us -> iPhDiscDistance:8’h10, wPhDiscDistance2M:4’h1, r2MphDiffAbsMax:10’h3F(63), wPhDiscDiffAbs:10’h2C, wPhDiscDiffCap:10’h2C Time us -> iPhDiscDistance:8’h10, wPhDiscDistance2M:4’h1, r2MphDiffAbsMax:10’h3F(63), wPhDiscDiffAbs:10’h48, wPhDiscDiffCap:10’h3F Understanding: Configured phase discriminator distance is used to limit phase values. In this scenario, if the phase values (wPhDiscDiffAbs = 0x48) is greater than the configured phase discriminator distance(r2MphDiffAbsMax=0x3F) then phase value will be assigned with configured value (wPhDiscDiffCap = r2MphDiffAbsMax= 0x3F).

PHDISC_DIST_UW (RW) EL_SLOW_TRK_CNTR_VAL_1M (Bit Position – 4:0) 0x646 mod_reg_el_slw_trk_cnt.c To check if the early late logic is applied after N adjustments if the configured value in the register is N-1. Ex : If a value 3 is programmed, then early late adjustments is applied after 4 consecutive forward/backward adjustments. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Scenario 1: Write and read PHDISC_DIST_UW with 0x003 such that early late adjustments are applied after 4 consecutive forward/backward adjustment. Scenario 2: Write and read PHDISC_DIST_UW with 0x005 such that early late adjustments are applied after 5 consecutive forward/backward adjustment.

Expected outcome: Time us -> iElSlwTrkCntrl:15’h3, wElSlwTrkThld1M:5’h3, wSamplAdjBwdSet:1’b1, rSmplAdjBwd:1’b1 (4 Consecutive backward adjustments can be observed) Understanding: Early late slow tracking counter value is configured with value 3 based on which early late adjustment is carried out after 4 consecutive backward/forward adjustments.

Expected outcome: Time us -> iElSlwTrkCntrl:15’h5, wElSlwTrkThld1M:5’h5, wSamplAdjFwdSet:1’b1, rSmplAdjFwd:1’b1 (6 Consecutive forward adjustments can be observed) Understanding: Early late slow tracking counter value is configured with value 5 based on which early late adjustment is carried out after 6 consecutive backward/forward adjustments.

PHDISC_DIST_UW (RW) EL_SLOW_TRK_CNTR_VAL_2M (Bit Position – 9:5) 0x646 mod_reg_el_slw_trk_cnt_2M.c To check if the early late logic is applied after N adjustments if the configured value in the register is N-1 for 2M. Ex : If a value 3 is programmed, then early late adjustments is applied after 4 consecutive forward/backward adjustments. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz. Scenario 1: Write and read PHDISC_DIST_UW with 0x0060 such that early late adjustments are applied after 4 consecutive forward/backward adjustment. Scenario 2: Write and read PHDISC_DIST_UW with 0x00C0 such that early late adjustments are applied after 5 consecutive forward/backward adjustment.

Expected outcome: Time us -> iElSlwTrkCntrl:15’h60, wElSlwTrkThld2M:5’h3, wSamplAdjFwdSet:1’b1, rSmplAdjFwd:1’b1 (4 Consecutive forward adjustments can be observed) Understanding: Early late slow tracking counter value is configured with value 3 based on which early late adjustment is carried out after 4 consecutive backward/forward adjustments.

Expected outcome: Time us -> iElSlwTrkCntrl:15’hC0, wElSlwTrkThld2M:5’h6, wSamplAdjBwdSet:1’b1, rSmplAdjBwd:1’b1 (7 Consecutive backward adjustments can be observed) Understanding: Early late slow tracking counter value is configured with value 6 based on which early late adjustment is carried out after 7 consecutive backward/forward adjustments.

EL_THRES_LW (RW) EL_SAMPLE_THRESHOLD (Bit Position – 15:0) 0x648 mod_reg_el_samp_mf_thrd.c To check if the configured sample threshold value adjusts the early late samples. EL_THRES_UW (RW) EL_MF_THRESHOLD (Bit Position – 15:0) 0x64A To check if with the configured Matched filter threshold value adjusts the early late samples. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz , Frequency Drift = 100KHz Scenario 1: Write and read EL_THRES_LW and EL_THRES_UW register with value 0xFFFF (EL_SAMP_THRESHOLD = 0xFFFF and EL_MF_THRESHOLD=0xFFFF which is the maximum value for both the bits). Scenario 2: Write and read EL_THRES_LW and EL_THRES_UW register with value 0x0000 (EL_SAMP_THRESHOLD = 0x0000 and EL_MF_THRESHOLD=0x0000 which is the maximum value for both the bits).

Expected outcome: Time us -> iELSampThres:16’h0000, iElMFThres:16’h0000, wElSumThresMet:1’b1,rSmplAdjFwd:1’b1 Understanding: Early sum and Late sum values are compared with the configured threshold (iElSampThres), and threshold met signal will be enabled when both the values are greater than the configured value. This threshold signal met will be further used to in forward and backward adjustment Matched filter average value is compared with the configured threshold value (iElMFThres) to adjust the forward and backward samples.

Expected outcome: Time us -> iELSampThres:16’hFFFF, iElMFThres:16’hFFFF, wElSumThresMet:1’b1,rSmplAdjBwd:1’b1 Understanding: Early sum and Late sum values are compared with the configured threshold (iElSampThres), and threshold met signal will be enabled when both the values are greater than the configured value. This threshold signal met will be further used to in forward and backward adjustment Matched filter average value is compared with the configured threshold value (iElMFThres) to adjust the forward and backward samples.

AFC_CHECKSUM_CONFIG_2 (RW) AFC_CHKSUM_NPCNTMAXV1_1M (Bit Position – 7:0) 0x696 mod_reg_afc_chksum_npcntmaxval1_1M.c To check if the configured value starts the checksum to qualify the estimated frequency offset value. Range 0x00 to 0x3F Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz , Frequency Drift = 100KHz 3. Write and read AFC_CHECKSUM_CONFIG_2 register with value 0x2F to start the AFC checksum to qualify the frequency offset estimation.

Expected outcome: Time us -> iAfcChkSumbNPCntMax1mVal1:8’h2F,wFreqCheckSumFail:1’b0, rFreqOff:14’h0000 Time us-> iAfcChkSumbNPCntMax1mVal1:8’h2F,wFreqCheckSumFail:1’b1, rFreqOff:14’h0137 Understanding: Whenever the NegPosCount is greater than the configured value the AFC checksum will start (wFreqCheckSumFail = 0 indicates that AFC checksum starts). wFreqCheckSumFail signal is used to avoid frequency correction when there is false preamble detection. Hence rFreqOffs = 0. Note: The value should be in the range 0x00 to 0x3F, if it exceeds the value then packet degradation can be observed.

AFC_CHECKSUM_CONFIG_2 (RW) AFC_CHKSUM_NPCNTMAXV1_2M (Bit Position – 15:8) 0x696 mod_reg_afc_chksum_npcntmaxval1_2M.c To check if the configured value starts the checksum to qualify the estimated frequency offset value. Range 0x00 to 0x1F Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz , Frequency Drift = 100KHz 3. Write and read AFC_CHECKSUM_CONFIG_2 register with value 0x0F00 to start the AFC checksum to qualify the frequency offset estimation.

Expected outcome: Time us -> iAfcChkSumbNPCntMax2mVal1:8’h0F,wFreqCheckSumFail:1’b0, rFreqOff:14’h0000 Time us-> iAfcChkSumbNPCntMax2mVal1:8’h0F,wFreqCheckSumFail:1’b1, rFreqOff:14’h0134 Understanding: Whenever the NegPosCount is greater than the configured value the AFC checksum will start (wFreqCheckSumFail = 0 indicates that AFC checksum starts). wFreqCheckSumFail signal is used to avoid frequency correction when there is false preamble detection. Hence rFreqOffs = 0. Note: The value should be in the range 0x00 to 0x1F, if it exceeds the value then packet degradation can be observed.

LR_PREAMB_CONFIG_EXT (RW) LR_PRE_PEAKEARCH_THLD [15:0] 0x62C mod_reg_pre_peak_search.c To check if the configured threshold value detects the positive and negative peak for LR. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write and read LR_PREAMB_CONFIG_EXT register with threshold value 0xDAA.

Expected Outcome: Time= us -> iLrPrePeakSrchThld = 16’hDAA, wLrPeakP = 1’b1 Time= us -> iLrPrePeakSrchThld = 16’hDAA, wLrPeakN = 1’b1 Understanding: The positive (wLrPeakP) and negative (wLrPeakN) peak for LR will be set when the calculated correlation value (wCorrValue for positive and wCorrValue2C for negative) is greater than the configured threshold value (iLrPrePeakSrchThld).

AFC_CNTL_UW (RW) PRE_SEARCH_THRESHOLD [11:0] 0x632 mod_reg_pre_search_thrd.c To check if the configured threshold value detects preamble correctly. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read AFC_CNTL_UW register with threshold value 0x0FA to check the correctness of the preamble detection. This is verified by checking the number of packets received. Scenario 2: Write and read AFC_CNTL_UW register with threshold value 0x0E to check the correctness of the preamble detection. This is verified by checking the number of packets received.

Expected Outcome: Time= us -> iPreSrchThres1M = 12’hFA, rPreSrchDone = 1’b1. Five packets are transmitted and one packet is received for threshold value 12’hFA. Time= us -> iPreSrchThres1M = 12’h0E, rPreSrchDone = 1’b1. Five packets are transmitted and all five packet are received for threshold value 12’h0E. Understanding: The configured preamble search threshold value (iPreSrchThres1M) is compared with calculated preamble search sample accumulated value (wPreSrchSampAcc) to set preamble search positive and negative peak (oPreSrchPeakP and oPreSrchPeakN) which detects the preamble.

FRQ_DRFT_CFG_UW (RW) FREQ_OFF_EST_ERR_FACTOR [14:12] 0x666 mod_reg_per_err_factor.c To check if the configured percentage of the Final estimated value is greater than the difference between Final and Middle frequency offset error estimation values. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write and read FRQ_DRFT_CFG_UW register with counter value 0x01 such that (Final – Mid ) < = (Final)/(2^N) condition is satisfied.

Expected Outcome: Time= us -> iPerFactor = 3’h01, wPhDiscVarAbs is assigned with Final/(2^N) (wFreqCorr/2) value for N = 1 (configured), wNegPosDiffAbs is assigned with (Final – Mid) difference value, wFreqOffs = 14’h00. Understanding: The frequency offset is estimated based on the condition (Final – Mid ) < = (Final)/(2^N). The difference value should be less than the configured percentage frequency offset error estimation value for the condition to be satisfied. Note: The counter ‘N’ should be configured with a value between 0x01 to 0x05. The counter value 0x02 is considered as default for frequency offset estimation for any other configuration.

FRQ_DRFT_CFG_UW (RW) LRC2CorrSumExtn 0x666 mod_reg_corr_sumext_LRC2 To check the number of samples to be considered for correlation during LRC2 frequency drift estimation. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read FRQ_DRFT_CFG_UW register with 0x9064 to enable LRC2CorrSumExtn bit in order to consider correlation sum of 16 samples. Scenario 2: Write and read FRQ_DRFT_CFG_UW register with 0x1064 to disable LRC2CorrSumExtn bit in order to consider correlation sum of 4 samples.

Expected Outcome: Time= us -> iLrC2CorrSumExtn = 1’b1, wLeftMask = 4’h00, wRightMask = 4’h0F (Sum of 16 samples) Time= us -> iLrC2CorrSumExtn = 1’b0, wLeftMask = 4’h06, wRightMask = 4’h09 (Sum of 4 samples) Understanding: The configured bit selects the correlation sum of 4 samples or 16 samples when disabled or enabled respectively. It is compared with the sample counter input for the matched filter correlation sum estimation.

ENH_PREAM_DET_LW (RW) ENHANCED_PREAM_DET_ENB, PRE_SRCH_PEAK_CNT_THSLD 0x698 mod_reg_enh_pream_det.c To check the enhanced preamble detection configuration functionality. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read ENH_PREAM_DET_LW register with 0x000B to enable ENHANCED_PREAM_DET_ENB bit and configure PRE_SRCH_PEAK_CNT_THSLD threshold value (0x05) to avoid the misdetection of the preamble peak for 1M. Write FRQ_DRFT_CFG2_UW register with 0xE00 to provide AFC estimation start delay from preamble peak detection specific to 1M. Scenario 2: Write and read ENH_PREAM_DET_LW register with 0x000A to disable ENHANCED_PREAM_DET_ENB bit and configure PRE_SRCH_PEAK_CNT_THSLD threshold value (0x05) to avoid the misdetection of the preamble peak for 1M.

Expected Outcome: Time= us -> iEnhancedPreamDetEnb = 1’b1, iPreSrchPeakCntThrld = 5’h02, iAfcDelayRef = 7’h07, wAfcDelayRef1M = 4’h04, wAfcDelayRef = 6’h04 Time= us -> iEnhancedPreamDetEnb = 1’b0, iPreSrchPeakCntThrld = 5’h02, iAfcDelayRef = 7’h07, wAfcDelayRef1M = 4’h07, wAfcDelayRef = 6’h07 Understanding: When iEnhancedPreamDetEnb bit is configured to enable enhanced preamble detection algorithm, the delay to start the frequency offset estimation (wAfcDelayRef) is determined by comparing the delay value (iAfcDelayRef) and the threshold value (iPreSrchPeakCntThrld). When the iEnhancedPreamDetEnb bit is disabled, the delay to start the frequency offset estimation (wAfcDelayRef) is provided with the delay value (iAfcDelayRef).

ENH_PREAM_DET_LW (RW) ENHANCED_EARLY_LATE_ENB 0x698 mod_reg_enh_el_alg_en.c To check if the enhanced early late algorithm is enabled or not. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read ENH_PREAM_DET_LW register with 0x0001 to enable ENHANCED_EARLY_LATE_ENB bit to enable the enhanced early late algorithm. Scenario 2: Write and read ENH_PREAM_DET_LW register with 0x0000 to disable ENHANCED_EARLY_LATE_ENB bit to disable the enhanced early late algorithm.

Expected Outcome: Time= us -> iEnhancedEarlyLateEnb = 1’b1, oPeakPosi = 6’h02 Time = us -> iEnhancedEarlyLateEnb = 1’b1, oPeakPosiEnb = 1’b1 Time= us -> iEnhancedEarlyLateEnb = 1’b0, oPeakPosi = 6’h00 Time = us -> iEnhancedEarlyLateEnb = 1’b0, oPeakPosiEnb = 1’b0 Understanding: When iEnhancedEarlyLateEnb bit is enabled, the enhanced early late algorithm is enabled and the positive peak enable (oPeakPosiEnb) and positive peak value (oPeakPosi) are set which are used for early late estimation. When the iEnhancedEarlyLateEnb bit is disabled, the enhanced early late algorithm is disabled and hence positive peak enable (oPeakPosiEnb) and positive peak value (oPeakPosi) are not set.

PHASE_CORR_CFG_LW (RW) PC_IN_SEL, PHASE_CORR_CTRL 0x69C mod_reg_pc_in_sel.c To check the functionality of select signal to provide input to phase correlator. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read PHASE_CORR_CFG_LW register with 0x2001 to enable PHASE_CORR_CTRL and PC_IN_SEL bits to provide LPF output as input to the phase correlator. Scenario 2: Write and read PHASE_CORR_CFG_LW register with 0x2000 to enable PHASE_CORR_CTRL and disable PC_IN_SEL bits to provide normalizer output as input to the phase correlator.

Expected Outcome: Time= us -> iPcInSel = 1’b1, wPcInPhase = iLpfInPhase Time= us -> iPcInSel = 1’b1, wPcInPhase = wNormInPhase Understanding: When iPcInSel bit is enabled, LPF output is provided as the input to the phase correlator. When iPcInSel bit is enabled, normalizer output is provided as the input to the phase correlator.

PHASE_CORR_CFG_LW (RW) PC_ENB, PHASE_CORR_CTRL 0x69C mod_reg_pc_enb.c To check if the phase correlator is enabled or not. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read PHASE_CORR_CFG_LW register with 0xF99F to enable PHASE_CORR_CTRL and PC_ENB bits in order to enable phase correlation. Scenario 2: Write and read PHASE_CORR_CFG_LW register with 0xF99E to enable PHASE_CORR_CTRL and disable PC_ENB bits in order to disable phase correlation.

Expected Outcome: Time= us -> iPcEnb = 1’b1, rLrPreMatchLvl = 1’b1, wPcEnb = 1’b1 Time= us -> iPcEnb = 1’b0, rLrPreMatchLvl = 1’b1, wPcEnb = 1’b0 Understanding: The phase correlation is enabled by enabling the configuration bit iPcEnb.

PHASE_CORR_CFG_LW (RW) IQ_SWTCH, PHASE_CORR_CTRL 0x69C mod_reg_iq_switch.c To check swapping IQ signals functionality in phase correlator module. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read PHASE_CORR_CFG_LW register with 0xF99F to enable PHASE_CORR_CTRL and IQ_SWTCH bits in order to enable swapping of IQ signals. Scenario 2: Write and read PHASE_CORR_CFG_LW register with 0xF997 to enable PHASE_CORR_CTRL and disable IQ_SWTCH bits in order to disable swapping of IQ signals.

Expected Outcome: Time= us -> iIQSwtch = 1’b0, inph_sync_w = inph_sel_w, quad_sync_w = quad_sel_w Time= us -> iIQSwtch = 1’b1, inph_sync_w = quad_sel_w, quad_sync_w = inph_sel_w Understanding: When the configuration bit is enabled, the IQ (Inphase and Quadrature) signals are swapped. When the configuration bit is disabled, the IQ (Inphase and Quadrature) signals are not swapped.

PHASE_CORR_CFG_LW (RW) INPH_ADJ, QUAD_ADJ, PHASE_CORR_CTRL 0x69C mod_reg_inph_quad_adj.c To check timing adjustment of Inphase and Quadrature signals by configuring the timing delay. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read PHASE_CORR_CFG_LW register with 0xF99F to enable PHASE_CORR_CTRL and provide timing delay (0x09) by setting INPH_ADJ, QUAD_ADJ bits of the register.

Expected Outcome: Time = us -> iInphAdj= 4’h09, iQuadAdj = 4’h09 Time = us -> inph_dly_r = 100’h*7818, inph_sel_w = 10’h046 ( delayed by 9 clock cycles). Time = us -> quad_dly_r = 100’h*D3B2, quad_sel_w = 10’h3CF ( delayed by 9 clock cycles). Understanding: The Inphase and quadrature signals are adjusted based on the delay value configured. (If iInphAdj = 4’h09, iQuadAdj = 4’h09 then the signals are delayed by 9 clock cycles).

PHASE_CORR_CFG_LW (RW) LPF_LSB_SFT_ENB_1M, LPF_LSB_SFT_ENB_2M, LPF_LSB_SFT_ENB_LR, PHASE_CORR_CTRL 0x69C mod_reg_lpf_enb.c To check if the LSB bits of LPF input signal are shifted by two when AGC has maximum gain. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read PHASE_CORR_CFG_LW register with 0xF99F to enable LPF_LSB_SFT_ENB_1M, LPF_LSB_SFT_ENB_2M, LPF_LSB_SFT_ENB_LR, PHASE_CORR_CTRL. Scenario 2: Write and read PHASE_CORR_CFG_LW register with 0x299F to enable PHASE_CORR_CTRL and disable enable LPF_LSB_SFT_ENB_1M, LPF_LSB_SFT_ENB_2M, LPF_LSB_SFT_ENB_LR.

Expected Outcome: Time= us -> iLpfLsbSftEnb = 1’b1, iAgcLnaGain = 2’h0, iAgcLpf1Gain = 2’h0, iAgcLpf2Gain = 4’h0, ShftOn = 1’b1, iCodedRateSel = 1’b0, wLpfInph = 12’hFF8 (2 bit shift of iLpfInPhase = 10’h3FE). Time= us -> iLpfLsbSftEnb = 1’b0, iAgcLnaGain = 2’h0, iAgcLpf1Gain = 2’h0, iAgcLpf2Gain = 4’h0, ShftOn = 1’b1, iCodedRateSel = 1’b0, wLpfInph = iLpfInPhase. Understanding: The Inphase and quadrature input signals for LPF will be shifted by 2 bits when iLpfLsbSftEnb bit is enabled and AGC gain is maximum.

AFC_CHECKSUM_CONFIG_1 (RW) AFC_FRECHECKSUM_THLD (Bit position – 15:0) 0x694 mod_reg_afc_checksum_thrshld.c To check the configured threshold value for AFC checksum qualifies the estimated frequency offset. Range 0x0000 to 0xFFFF. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset = 300KHz and Frequency Drift =100kHz. Scenario 1: Write and read AFC_CHECKSUM_CONFIG_1 register with threshold value 0x0000. Scenario 2: Write and read AFC_CHECKSUM_CONFIG_1 register with threshold value 0x0700. Scenario 3: Write and read AFC_CHECKSUM_CONFIG_1 register with threshold value 0xFFFF.

Expected Outcome: Time= us, iAfcCheckSumThld:16’h0000, wFreqCheckSumFail: 1’b0, rFreqOff:14’h13B Understanding: Estimated frequency checksum will be compared with the configured threshold value. AFC checksum estimation will qualify (wFreqCheckSumFail = 0) for Frequency offset whenever the estimated checksum is greater than configured threshold value. In this scenario, since threshold value is 0x0000 checksum estimation will qualify for Frequency offset estimation (All packets received).

Expected Outcome: Time = us iAfcCheckSumThld:16’h0700, wFreqCheckSumFail: 1’b0, rFreqOff:14’h15B Understanding: Estimated frequency checksum will be compared with the configured threshold value. AFC checksum estimation will qualify (wFreqCheckSumFail = 0) for Frequency offset whenever the estimated checksum is greater than configured threshold value. In this scenario, threshold value is 0x0700 checksum estimation will qualify for Frequency offset estimation(All packets received).

Expected Outcome: Time = us, iAfcCheckSumThld:16’hFFFF , wFreqCheckSumFail: 1’b1, rFreqOff:14’h0000 Understanding: Estimated frequency checksum will be compared with the configured threshold value. AFC checksum estimation will qualify (wFreqCheckSumFail = 0) for Frequency offset whenever the estimated checksum is greater than configured threshold value. In this scenario, since threshold value is 0xFFFF(maximum) checksum estimation will not qualify for Frequency offset estimation (Packet loss can be observed since configured threshold value is more. No packet is received).

ENH_PREAM_DET_UW (RW) ADJ_MAX_VAL1_CNT (Bit position – 7:0) 0x69A mod_reg_adj_max_val1_cnt_1M.c To check if the configured value adjusts the wNPCountMaxVal1 which is used in Enhanced preamble detection. Configured should be always less than wNPCountMaxVal1. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset = 300KHz and Frequency Drift =100KHz. Scenario 1: Write and read ENH_PREAM_DET_UW register with threshold value 0x0000. Scenario 2: Write and read ENH_PREAM_DET_UW register with threshold value 0x000E.

Expected Outcome: Time = us, iAdjMaxVal1Cnt:8’h00 , wNPCountMaxVal1:8’h1F, rNegPosCount:8’h01 Time = us, iAdjMaxVal1Cnt:8’h00 , wNPCountMaxVal1:8’h1F, rNegPosCount:8’h1F Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal1 is assigned to rPosNegCount. In this scenario, rNegPosCount == wNPCountMaxVal1 (iAdjMaxVal1 =0). Enhanced preamble detection depends on the adjusted value.

Expected Outcome: Time = us, iAdjMaxVal1Cnt:8’h0E , wNPCountMaxVal1:8’h1F, rNegPosCount:8’h01 Time = us, iAdjMaxVal1Cnt:8’h0E , wNPCountMaxVal1:8’h1F, rNegPosCount:8’h11 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal1 is assigned to rPosNegCount. In this scenario, rNegPosCount == wNPCountMaxVal1 - iAdjMaxVal1 = 0x11 Enhanced preamble detection depends on the adjusted value.

ENH_PREAM_DET_UW (RW) ADJ_MAX_VAL2_CNT (Bit position – 15:8) 0x69A mod_reg_adj_max_val2_cnt_1M.c To check if the configured value adjusts the wNPCountMaxVal2 which is used in Enhanced preamble detection. Configured should be always less than wNPCountMaxVal2. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset = 300KHz and Frequency Drift =100kHz. Scenario 1: Write and read ENH_PREAM_DET_UW register with threshold value 0x0000. Scenario 2: Write and read ENH_PREAM_DET_UW register with threshold value 0x0E00.

Expected Outcome: Time = us, iAdjMaxVal2Cnt:8’h00 , wNPCountMaxVal2:8’h3F, wNegPosCount:8’h19, PosPreaCount:2’h1 Time = us, iAdjMaxVal2Cnt:8’h00 , wNPCountMaxVal2:8’h3F, wNegPosCount:8’h35, PosPreaCount:2’h2 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal2 is compared with the wNegPosCount. Based on wNegPosCount, positive and negative preamble peak count will be calculated.

Expected Outcome: Time = us, iAdjMaxVal2Cnt:8’h0E , wNPCountMaxVal2:8’h3F, wNegPosCount:8’h0D, PosPreaCount:2’h1 Time = us, iAdjMaxVal2Cnt:8’h0E , wNPCountMaxVal2:8’h3F, wNegPosCount:8’h40, PosPreaCount:2’h1 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal2 is compared with the wNegPosCount. Based on wNegPosCount, positive and negative preamble peak count will be calculated.

ENH_PREAM_DET_UW (RW) ADJ_MAX_VAL1_CNT (Bit position – 7:0) 0x69A mod_reg_adj_max_val1_cnt_2M.c To check if the configured value adjusts the wNPCountMaxVal1 which is used in Enhanced preamble detection. Configured should be always less than wNPCountMaxVal1. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset = 300KHz and Frequency Drift =100kHz. Scenario 1: Write and read ENH_PREAM_DET_UW register with threshold value 0x0000. Scenario 2: Write and read ENH_PREAM_DET_UW register with threshold value 0x000E.

Expected Outcome: Time = 871.5us, iAdjMaxVal1Cnt:8’h00, wAdjMaxVal1Cnt2m:8’h00,wNPCountMaxVal1:8’h0F, rNegPosCount:8’h01 Time = us, iAdjMaxVal1Cnt:8’h0, wAdjMaxVal1Cnt2m:8’h00,wNPCountMaxVal1:8’h0F, rNegPosCount:8’h0F Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal1 is assigned to rPosNegCount. In this scenario, rNegPosCount == wNPCountMaxVal1 (wAdjMaxVal1Cnt2m =0). Enhanced preamble detection depends on the adjusted value.

Expected Outcome: Time = us, iAdjMaxVal1Cnt:8’h0E, wAdjMaxVal1Cnt2m:8’h07, wNPCountMaxVal1:8’h0F, rNegPosCount:8’h01 Time = us, iAdjMaxVal1Cnt:8’h0E, wAdjMaxVal1Cnt2m:8’h07, wNPCountMaxVal1:8’h0F, rNegPosCount:8’h08 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal1 is assigned to rPosNegCount. In this scenario, rNegPosCount == wNPCountMaxVal1 - wAdjMaxVal1Cnt2m= 0x08 Enhanced preamble detection depends on the adjusted value.

ENH_PREAM_DET_UW (RW) ADJ_MAX_VAL2_CNT (Bit position – 15:8) 0x69A mod_reg_adj_max_val2_cnt_2M.c To check if the configured value adjusts the wNPCountMaxVal2 which is used in Enhanced preamble detection. Configured should be always less than wNPCountMaxVal2. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset = 300KHz and Frequency Drift =100kHz. Scenario 1: Write and read ENH_PREAM_DET_UW register with threshold value 0x0000. Scenario 2: Write and read ENH_PREAM_DET_UW register with threshold value 0x0E00.

Expected Outcome: Time = us, iAdjMaxVal2Cnt:8’h00 , wNPCountMaxVal2:8’h1F, wNegPosCount:8’h03, PosPreaCount:2’h1 Time = us, iAdjMaxVal2Cnt:8’h00 , wNPCountMaxVal2:8’h1F, wNegPosCount:8’h10, PosPreaCount:2’h1 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal2 is compared with the wNegPosCount. Based on wNegPosCount, positive and negative preamble peak count will be calculated.

Expected Outcome: Time = us, iAdjMaxVal2Cnt:8’h0E,wAdjMaxVal2Cnt2m:8’h07, wNPCountMaxVal2:8’h1F, wNegPosCount:8’h09, PosPreaCount:2’h1 Time = us, iAdjMaxVal2Cnt:8’h0E,wAdjMaxVal2Cnt2m:8’h07,wNPCountMaxVal2:8’h1F, wNegPosCount:8’h20, PosPreaCount:2’h2 Understanding: Adjustment will happen only when Enhanced Preamble Detection is Enabled. Difference of configured value and wNPCountMaxVal2 is compared with the wNegPosCount. Based on wNegPosCount, positive and negative preamble peak count will be calculated.

PHASE_CORR_CFG_UW (RW) 1. EL_FULL_PKT_TRK_2M (Bit position – 1) 2. EL_SLOW_TRK_ENB_2M (Bit position – 2) 3. EL_SAMP_ADJ_2M (Bit position – 4) 4. EL_CTRL_2M (Bit position – 5) 0x69E mod_reg_el_func_ctrl_2M.c To check early late functionality for 2M: EL_FULL_PKT_TRK - Early late tracking for full packet. EL_SLOW_TRK_ENB - Early late slow tracking for payload. EL_SAMP_ADJ - Early late sampling point adjustment. EL_CTRL - Early late sum comparison. Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0x00CA to disable the above mentioned register bits. Write PHASE_CORR_CFG_UW register with value 0x00FC to enable the above mentioned register bits.

Expected outcome: 1. Time: us -> iElCtrl:1’b0, iElSampAdj:1’b0, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 0: When Early sum or Late sum value is greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =0: Samples will be adjusted based on Early Late threshold condition.(Matched Filter average threshold condition will not be checked).

Expected outcome: 1. Time: us -> iElCtrl:1’b1, iElSampAdj:1’b1, wElSumThresMet:1’b1, rSamplAdjFwd:1’b0, rSamplAdjBwd:1’b1 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 1: Both Early sum and Late sum value must be greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =1: Samples will be adjusted based on Early late threshold met and matched filter average threshold.(Matched Filter average threshold condition will be checked).

PHASE_CORR_CFG_UW (RW) NORM_PH_CTRL_2M (Bit position – 6) 0x69E mod_reg_norm_ph_ctrl_2M.c To check the Normalizer input data selection for 2M 0 - Selects the input data 1 - Selects the registered input data Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0xEC to select the registered input data. Write PHASE_CORR_CFG_UW register with value 0xAC to select the input data.

Expected outcome: Time: us ->iNormPhaseCtrl:1’b1, Output signal: wNormInPhase_sel = NormInPhase_q Case 2: NORM_PH_CTRL bit disabled 1. Time: us -> iNormPhaseCtrl:1’b0, Output signal: wNormInPhase_sel = iNormInPhase Understanding: NORM_PH_CTRL: Normalizer input data selection bit. NORM_PH_CTRL = 0, select the incoming input data NORM_PH_CTRL = 1, select the registered input data. To synchronize with the clock.

PHASE_CORR_CFG_UW (RW) FREQ_CHCK_SUM_2M (Bit position – 7) 0x69E mod_reg_chksum_enb_2M.c To check enabling/disabling of frequency check sum feature for 2M. 0 - Disable 1 - Enable Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0xEC to enable the frequency check sum feature. Write PHASE_CORR_CFG_UW register with value 0x6C to disable the frequency check sum feature.

Case 1: FREQ_CHCK_SUM bit enabled
Expected outcome: Time: us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0000 Time: us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b1,wFreqOffs:14’h0000 Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 1, compare the estimated checksum value with threshold value. wFreqCheckSumFail signal will be enabled/disabled based on the comparison. This signal is used to avoid frequency correction when there is false preamble detection. Hence FreqOffs = 0.

Case 2: FREQ_CHCK_SUM bit disabled
Expected outcome: Time: us -> iFreqCheckSumEnb: 1’b0, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h012C Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 0, wFreqCheckSumFail will remain low and frequency correction will be carried out even for false preamble detection (FreqOffs = 12C)

PHASE_CORR_CFG_UW (RW)
Register Name Register Address (16 – Bit) Test Case ID Purpose PHASE_CORR_CFG_UW (RW) 1. EL_FULL_PKT_TRK_LR (Bit position – 8) 2. EL_SLOW_TRK_ENB_LR (Bit position – 10) 3. EL_SAMP_ADJ_LR (Bit position – 12) 4. EL_CTRL_LR (Bit position – 13) 0x69E mod_reg_el_func_ctrl_LR.c To check early late functionality for 2M: EL_FULL_PKT_TRK - Early late tracking for full packet. EL_SLOW_TRK_ENB - Early late slow tracking for payload. EL_SAMP_ADJ - Early late sampling point adjustment. EL_CTRL - Early late sum comparison. Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0xFC00 to enable the above mentioned register bits. Write PHASE_CORR_CFG_UW register with value 0x0100 to disable the above mentioned register bits.

Expected outcome: 1. Time: us -> iElCtrl:1’b1, iElSampAdj:1’b1, wElSumThresMet:1’b1, rSamplAdjFwd:1’b0, rSamplAdjBwd:1’b1 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 1: Both Early sum and Late sum value must be greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =1: Samples will be adjusted based on Early late threshold met and matched filter average threshold.(Matched Filter average threshold condition will be checked).

Expected outcome: 1. Time: us -> iElCtrl:1’b0, iElSampAdj:1’b0, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 0: When Early sum or Late sum value is greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =0: Samples will be adjusted based on Early Late threshold condition.(Matched Filter average threshold condition will not be checked).

PHASE_CORR_CFG_UW (RW) NORM_PH_CTRL_LR (Bit position – 14) 0x69E mod_reg_norm_ph_ctrl_2M.c To check the Normalizer input data selection for 2M 0 - Selects the input data 1 - Selects the registered input data Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0xEC00 to select the registered input data. Write PHASE_CORR_CFG_UW register with value 0xAC00 to select the input data.

Expected outcome: Time: us ->iNormPhaseCtrl:1’b1, Output signal: wNormInPhase_sel = NormInPhase_q Case 2: NORM_PH_CTRL bit disabled Expected outcome: 1. Time: us -> iNormPhaseCtrl:1’b0, Output signal: wNormInPhase_sel = iNormInPhase Understanding: NORM_PH_CTRL: Normalizer input data selection bit. NORM_PH_CTRL = 0, select the incoming input data NORM_PH_CTRL = 1, select the registered input data. To synchronize with the clock.

RXFUNC_CNTL_LW (RW) SAT_PH_DIFF_ENB_1M (Bit position – 3) 0x61C mod_reg_sat_phase_disc_enb_1M.c To check if the saturated phase discriminator output is used or not Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CNTL_LW register with value 0x3F7F to enable saturated phase discriminator output. Write RXFUNC_CNTL_LW register with value 0x3F77 to disable saturated phase discriminator output.

Expected outcome: Time: us -> iSatPhDiscDiffEn:1’b0, Output signal: wPhDisDiffSat = wPhDiscDiffMod. Time: us -> iSatPhDiscDiffEn:1’b1, Output signal: wPhDisDiffSat = r1MPhDiffAbsMax. Understanding: When iSatPhDiscDiffEn bit is enabled, the phase discriminator output is assigned with the maximum phase difference value (r1MPhDiffAbsMax). When iSatPhDiscDiffEn bit is disabled, the phase discriminator output is assigned with the calculated phase difference value (wPhDiscDiffMod).

PHASE_CORR_CFG_UW(RW) SAT_PH_DIFF_ENB_2M (Bit position – 3) 0x69E mod_reg_sat_phase_disc_enb_2M.c To check if the saturated phase discriminator output is used or not for 2M. Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0x3FFF to enable saturated phase discriminator output. Write PHASE_CORR_CFG_UW register with value 0x3FF7 to disable saturated phase discriminator output.

PHASE_CORR_CFG_UW(RW) SAT_PH_DIFF_ENB_LR (Bit position – 11) 0x69E mod_reg_sat_phase_disc_enb_LR.c To check if the saturated phase discriminator output is used or not for LR. Description: Set attenuation value = -85 dBm at BT1 side. Write PHASE_CORR_CFG_UW register with value 0x3FFF to enable saturated phase discriminator output. Write PHASE_CORR_CFG_UW register with value 0x37FF to disable saturated phase discriminator output.

ENH_PREAM_DET_LW (RW) ENHANCED_PREAM_DET_ENB, PRE_SRCH_PEAK_CNT_THSLD 0x698 mod_reg_enh_pream_det_2M.c To check the enhanced preamble detection configuration functionality for 2M. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Scenario 1: Write and read ENH_PREAM_DET_LW register with 0x000B to enable ENHANCED_PREAM_DET_ENB bit and configure PRE_SRCH_PEAK_CNT_THSLD threshold value (0x05) to avoid the misdetection of the preamble peak for 2M. Write FRQ_DRFT_CFG2_UW register with 0xE00 to provide AFC estimation start delay from preamble peak detection specific to 2M. Scenario 2: Write and read ENH_PREAM_DET_LW register with 0x000A to disable ENHANCED_PREAM_DET_ENB bit and configure PRE_SRCH_PEAK_CNT_THSLD threshold value (0x05) to avoid the misdetection of the preamble peak for 2M.

Expected Outcome: Time= us -> iEnhancedPreamDetEnb = 1’b1, wPreSrchPeakCntThsld2m = 5’h01, iAfcDelayRef = 7’h70, wAfcDelayRef =6’h05, wAfcDelayRef2M=6’h05 Time= us -> iEnhancedPreamDetEnb = 1’b0, wPreSrchPeakCntThsld2m = 5’h01, iAfcDelayRef = 7’h70, wAfcDelayRef = 6’h07, wAfcDelayRef2M = 3’h7 Understanding: When iEnhancedPreamDetEnb bit is configured to enable enhanced preamble detection algorithm, the delay to start the frequency offset estimation (wAfcDelayRef) is determined by comparing the delay value (iAfcDelayRef) and the threshold value (wPreSrchPeakCntThsld2m). When the iEnhancedPreamDetEnb bit is disabled, the delay to start the frequency offset estimation (wAfcDelayRef) is provided with the delay value (iAfcDelayRef).

MODEM REGISTER VERIFICATION

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MODEM REGISTER VERIFICATION

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