1. Geoff Gunow and Sara Sinback (geogunow, sinback)
6.175 Final Presentation
Geoff Gunow and Sara Sinback
(geogunow, sinback)

2. Progress
We finished Part 1 and Part 2 of the project. Now, we have developed working three-cycle and six-stage pipelined multicore RISC V processors. In each core, these processors have the store queue and Loaded Hit Under Store Miss optimizations implemented.

3. Part 2 - Multicore I.P.C. for Multiply2 benchmark
Results
Part 1 - Store Queue I.P.C.
Part 2 - Multicore I.P.C. for Multiply2 benchmark
Benchmark
Cache / Store Queue
L.H.U.S.M.
Difference
Median
0.46
0.49
+0.03
Multiply
0.61
0.62
+0.01
Qsort
0.32
0.33
Tower
0.27
0`48
+0.21
Vvad
0.47
0.53
+0.06
Version
Instructions
Cycles
IPC
threecache
55652
91468
0.61
sixcache
55721
60034
0.93
threestq
55669
91814
sixstq
55670
60326
0.92
threelhusm
55656
88812
0.62
sixlhusm
55661
57077
0.98

4. Unfinished Work
Started implementing a thread-safe lock-free linked list using load reserve and store conditional but encountered issues with both the software (harder than I remembered) and assembly syntax
HEAD

5. Difficulties encountered
Debugging load hit under store miss
Bug was very infrequent, only the cache benchmark failed
Issue was not searching the store queue before the cache during a load miss

6. Difficulties encountered
After integrating full memory hierarchy: stress tests failed.
Debugging output suggested Core 3 was deadlocked with another core.
Log inspection showed that other cores were doing fine (did not appear deadlocked)
Realized that since the DCache for Core 3 was being serviced with minimal priority, we needed to give caches first priority on some kind of rotating basis.
Changed our DCache servicing protocol in the Message Router to be round-robin style; problem resolved

7. Difficulties encountered
Again, debugging load hit under store miss (part 2)
A changed ordering of rules from part 1 caused out load hit rule to take precedence over load miss, causing deadlock
Solved by adding a boolean register for load miss and using it as a guard for the load hit rule

8. Improvements for the course
Many benchmarks not intuitive, which makes debugging frustrating; a short lab where we write our own assembly benchmarks could make parsing benchmarks easier (especially for students with limited or no prior experience using assembly languages). Should come early, but could easily replace, eg. Lab 8 (exceptions lab), or something.