1. De-synchronization: from synchronous to asynchronous
Based on the paper:
Blunno, Cortadella, Kondratyev, Lavagno, Lwin, Sotiriou,
Handshake protocols for de-synchronization,
ASYNC 2004.

2. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

3. Asynchronous
De-synchronize
CLK
Synchronous
CLK

4. Synchronous circuit
MS flip-flop L L L L 1 1
CLK L L

5. De-synchronization L L L L 1 1 C L L

6. De-synchronization
Distributed controllers substitute the clock network C C C C C C
The data path remains intact !

7. Design flow Think synchronous
Design synchronous: one clock and edge-triggered flip-flops
De-synchronize (automatically)
Run it asynchronously

8. Prior work Micropipelines (Sutherland, 1989)
Local generation of clocks
Varshavsky et al., 1995
Kol and Ginosar, 1996
Theseus Logic (Ligthart et al., 2000)
Commercial HDL synthesis tools
Direct translation and special registers
Phased logic (Linder and Harden, 1996) (Reese, Thornton, Traver, 2003)
Conceptually similar
Different handshake protocol (2 phase vs. 4 phase)

9. Automatic de-synchronization
Devise an automatic method for de-synchronization
Identify a subclass of synchronous circuits suitable for de-synchronization
Formally prove correctness

10. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

13. Synchronous flow

24. De-synchronized flow

26. +

37. Flow equivalence
[Guernic, Talpin, Lann, 2003]

38. A B

39. De-synchronized behavior
Flow equivalence
CLK A B
Synchronous behavior A B
De-synchronized behavior

40. De-synchronized behavior
Flow equivalence
CLK A B
Synchronous behavior A B
De-synchronized behavior

41. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

42. L L L L 1 1 C L L

43. C C C C C C

44. L C

45. A B C D
A B C D-
A B C D+
A latch cannot read another data item until the successor has captured the current one

46. A B 1 C D
A B C D-
A B C D+
A latch cannot read another data item until the successor has captured the current one

47. A B C D
A B C D-
A B C D+
A latch cannot read another data item until the successor has captured the current one

48. A 1 B C D
A B C D-
A B C D+
A latch cannot read another data item until the successor has captured the current one

49. A B C D
A B C D-
A B C D+

50. A B C D 1
A B C D-
A B C D+

51. A B C D
A B C D-
A B C D+

52. A B C 1 D
A B C D-
A B C D+
A latch cannot become opaque before having captured the data item from its predecessor

53. A B 1 C 1 D
A B C D-
A B C D+
A latch cannot become opaque before having captured the data item from its predecessor

54. A B C 1 D
A B C D-
A B C D+
A latch cannot become opaque before having captured the data item from its predecessor

55. A B C D
A B C D-
A B C D+
A latch cannot become opaque before having captured the data item from its predecessor

56. A B C D
A B C D-
A B C D+

57. A B C D
A B C D+
A B C D- A B

58. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

59. Can we increase concurrency ?
A B+
A B-
A B+
A B-
A B+
A B-
not flow-equivalent

60. A B A B
data overrun A B
data lost

61. Can we reduce concurrency ? How much ?
A B+
A B-
Can we reduce concurrency ? How much ?

62. A B+
A B-
(8 states)
A B+
A B-
A B+
A B-
(6 states)
A B+
A B-
(5 states)
A B+
A B-
(4 states)

63. A B
de-synchronization
model A B A B
fully decoupled
(Furber & Day)
GasP, IPCMOS A B
semi-decoupled
(Furber & Day) A B A B
simple 4-phase
non-overlapping

64. A B+
A B-
A B+
A B-
de-synchronization
model
A B+
A B-
A B+
A B-
fully decoupled
(Furber & Day)
GasP, IPCMOS
simple 4-phase
non-overlapping
A B+
A B-
A B+
A B-
semi-decoupled
(Furber & Day)

65. 4-phase latch controllersLt Lt
Rin
Rout
Rin
Rout
Ain
Aout
Ain
Aout
Furber and Day, IEEE Trans. VLSI, June 1996
Implementation note: Lt=0 (transparent), Lt=1 (opaque)

66. 4-phase latch controllers
Rin+
Rout+
Lt+
Ain+
Aout+ ? Lt
Rin-
Rin
Rout
Rout-
Lt-
Ain
Aout
Ain-
Aout-

67. 4-phase latch controllers
Rin+
Rout+
Ain+
Lt+
Aout+ Lt
Rin-
Rout-
Rin
Rout
Ain
Aout
Ain-
Lt-
Aout-
Simple 4-phase controller

68. 4-phase latch controllers
Rin+
Rout+
Ain+
Lt+
Aout+
Rin-
Rout-
Ain-
Lt-
Aout-
Simple 4-phase controller

69. 4-phase latch controllers
Rin+ A+
Rout+
Ain+
Lt+
Aout+ Lt
Rin- A-
Rout-
Rin
Rout
Ain
Aout
Ain-
Lt-
Aout-
Semi-decoupled controller

70. 4-phase latch controllers
Rin+ A+
Rout+
Ain+
Lt+
Aout+
Rin- A-
Rout-
Ain-
Lt-
Aout-
Semi-decoupled controller

71. 4-phase latch controllers
Rin+ A+
Rout+
Ain+
Lt+
Aout+ B+ Lt
Rin- A-
Rout-
Rin
Rout
Ain
Aout
Ain-
Lt-
Aout- B-
Fully decoupled controller

72. 4-phase latch controllers
Rin+ A+
Rout+
Ain+
Lt+
Aout+ B+
Rin- A-
Rout-
Ain-
Lt-
Aout- B-
Fully decoupled controller

73. 4-phase latch controllers (state graphs)
Semi-decoupled controller
Fully decoupled controller

74. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
Ri A Rx B Ro+
Ai Ax Ao+
Ri A Rx B Ro-
Ai Ax Ao-
(semi-decoupled 4-phase protocol)

75. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

76. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

77. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

78. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

79. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

80. (semi-decoupled 4-phase protocol)B Rx Ri Ro
cntrl
cntrl Ax Ai Ao
A B-
A B+
(semi-decoupled 4-phase protocol)

81. A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-

82. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

84. Which protocols are valid for de-synchronization ?

85. Theorem: the de-synchronization protocol preserves flow-equivalence
A B+
A B-
Theorem: the de-synchronization protocol preserves flow-equivalence
Proof: by induction on the length of the traces
Induction hypothesis: same latch values at reset
Induction step:
same values at cycle i  same values at cycle i+1

86. A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-

87. Theorem: any reduction in concurrency preserves flow-equivalence
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-
A B+
A B-

88. Any hybrid approach preserves flow-equivalence !
Semi-
decoupled
Fully
decoupled
non-
overlapping

89. A B C D
A B C D+
A B C D-

90. Flow-equivalence is preserved, … but …
A B C D+
A B C D-
semi- decoupled
non- overlapping
fully decoupled
Flow-equivalence is preserved, … but …

91. Liveness
Preservation of flow-equivalence: all the generated traces are equivalent
Are all traces generated ? (Is the marked graph live ?) Not always !

92. Semi-decoupled 4-phase handshake protocol
A B C D+
A B C D-
Semi-decoupled 4-phase handshake protocol
Liveness: all cycles have at least one token [Commoner 1971]

93. Simple 4-phase handshake protocol
A B C D+
A B C D-
Simple 4-phase handshake protocol

94. Results about liveness
At least three latches in a ring are required with only one data token circulating [Muller 1962]
Theorem (this paper): any hybrid combination of protocols is live if the simple 4-phase protocol is not used Proof: any cycle has at least one token

95. Valid for de-synchronization A+ B+ A- B- A+ B+ A- B-
model
A B+
A B-
A B+
A B-
fully decoupled
(Furber & Day)
GasP, IPCMOS
simple 4-phase
non-overlapping
A B+
A B-
A B+
A B-
semi-decoupled
(Furber & Day)

96. Outline What is de-synchronization ? Behavioral equivalence
4-phase protocols for de-synchronization
Concurrency
Correctness
An example

98. Async DLX block diagram

99. = Synchronous RTL Synchronous Desynchronized
Cycle: ns
Power: mW
Area: 372,656m
Cycle: ns
Power: mW
Area: 378,058m
All numbers are after Placement & Routing
Total of 1500 flip-flops, 3000 latches
DE-SYNC design includes 5 controllers, each driving 2 clock trees
Power numbers include the clock tree
Technology: UCM/Virtual Silicon 0.18 µm

100. Discussion
The de-synchronization model provides an abstraction of the timing behavior

101. Exploration of the design space
[2,3]
[1,2]
[8,9]
[5,7]
[3,5]
[2,4] A B E F G C D
[0,0]
[3,5]
[5,7]
[2,3]
[2,4]
[1,2]
[8,9]
Timing analysis
Exploration of the design space

102. Conclusions
EDA tools require a formal support (they must work for all circuits)
A complete characterization of 4-phase protocols has been presented (partial order based on concurrency)
Design flow developed at Cadence Berkeley Labs
Automated from gate netlist
Static timing analysis to derive matched delays
Constrained P&R to meet timing constraints