1. Introduction to Logic Synthesis
Alan Mishchenko
UC Berkeley

2. Overview Fundamentals Computations in logic synthesis
Boolean functions and their representations
Two aspects: functionality and structure
Logic synthesis and optimization
Computations in logic synthesis
Traversal, windowing, structural cuts
Simulation, SAT solving
And-Inverter Graphs (AIGs)
AIG-based synthesis, mapping, verification

3. Boolean Variables Boolean variable x takes values 0 or 1
If the value is not known, is is called don’t-care, which is denoted as symbol dash (-)
Value 0
Value 1 No
Yes
False
True
Yin
Yang

4. Boolean Functions
Boolean function (or logic function) is a function having Boolean input and output variables
For example, f = F(a, b, c) takes three Boolean inputs, a, b, c, and produces Boolean output, f
There are 8 possible input combinations:
000, 001, 010, 011, 100, 101, 110, 111 f F a b c

5. On-set, Off-set, and DC-setab 00 01 11 10 1
Completely specified logic function
Incompletely specified logic function cd ab 00 01 11 10 1  cd 00 01 11 10 1 00 01 11 10 1 00 01 11 10 1
On-set
Off-set
DC-set

6. Boolean Operators
These are elementary functions taking one or two inputs and producing one output 1 1
Buffer
Inverter (! or ‘) 1 1 1
AND (*)
OR (+)
XOR ()

7. Representations F = ab+cd F = (a+c)(a+d)(b+c)(b+d) Truth table (TT)
Sum-of-products (SOP)
Product-of-sums (POS)
Binary decision diagram (BDD)
And-inverter graph (AIG)
Logic network (LN)
abcd F
0000
0001
0010
0011 1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 a b c d F 1 a b c d F a b c d F ab
x+cd
F = ab+cd
F = (a+c)(a+d)(b+c)(b+d)

8. Representation Overview
TT are the natural representation of logic functions
Not practical for large functions
Still good for functions up to 16 variables
SOP is widely used in synthesis tools since 1980’s
More compact than TT, but not canonical
Can be efficiently minimized (SOP minimization by Espresso, ISOP computation) and translated into multi-level forms (algebraic factoring)
BDD is a useful representation discovered around 1986
Canonical (for a given function, there is only one BDD)
Very good, but only if (a) it can be constructed, (b) it is not too large
Unreliable (non-robust) for many industrial circuits
AIG is an up-and-coming representation!
Compact, easy to construct, can be made “canonical” using a SAT solver
Unifies the synthesis/mapping/verification flow

9. Historical Perspective
Problem Size
ABC
100000
SIS, VIS, MVSIS
100
Espresso, MIS, SIS 50
AIG 16
SOP
BDD
CNF TT
1980
1990
2000
Time

10. Two Aspects of Representations
Boolean functions have two aspects
Functionality (as a table or diagram)
Truth table, Binary Decision Diagram, etc
Structure (as a network of operators)
AIG, logic network, mapped netlist, etc

11. Representations F = ab+cd F = (a+c)(a+d)(b+c)(b+d) Truth table (TT)
Sum-of-products (SOP)
Product-of-sums (POS)
Binary decision diagram (BDD)
And-inverter graph (AIG)
Logic network (LN)
abcd F
0000
0001
0010
0011 1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 a b c d F 1 a b c d F a b c d F ab
x+cd
F = ab+cd
F = (a+c)(a+d)(b+c)(b+d)

12. What is Logic Synthesis?
Logic synthesis is applied to Boolean functions
It has two goals
If functionality is given, transform it into structure
If structure is given, optimize it
Optimization is transformation to improve some aspect (number of nodes, levels, etc)

13. What are Typical Transformations?
For SOP, minimize cubes/literals
For BDD, minimize nodes/width
For AIG, restructure, minimize nodes/levels
For LN, restructure, minimize area/delay

14. Computations in Logic Synthesis
Divide-and-conquer
Example: traversal, windowing, cut computation
Guess-and-check
Example: bit-wise simulation
Reason-and-prove
Example: Boolean satisfiability

15. Terminology Boolean function (e.g. F = ab+cd) Boolean network
Variables (e.g. b)
Minterms (e.g. abcd)
Cube (e.g. ab)
Boolean network
Primary inputs/outputs
Logic nodes
Fanins/fanouts
Transitive fanin/fanout cone
Cut and window (defined later)
Primary inputs
Primary outputs
Fanins
Fanouts
TFO
TFI

16. Traversal Traversal is visiting nodes in the network in some order
Topological order visits nodes from PIs to POs
Each node is visited after its fanins are visited
Reverse topological order visits nodes from POs to PIs
Each node is visited after its fanouts are visited
Primary outputs 8 3 7 2 6 1 5 4
Primary inputs
Traversal in a topological order

17. Windowing Definition A window includes
A window for a node is the node’s context, in which an operation is performed
A window includes
k levels of the TFI
m levels of the TFO
all re-convergent paths between window PIs and window POs
Window POs
Window PIs
k = 3
m = 3
Pivot node

18. Structural Cuts in AIG a b c p q n
A cut of a node n is a set of nodes in transitive fan-in
such that
every path from the node to PIs is blocked by nodes in the cut.
A k-feasible cut means the size of the cut must be k or less.
The set {p, b, c} is a 3-feasible cut of node n. (It is also a 4-feasible cut.)
k-feasible cuts are important in FPGA mapping because the logic between root n and the cut nodes {p, b, c} can be replaced by a k-LUT

19. Cut Computation a b c p q { {p}, {a, b} } { {q}, {b, c} } { {a} }
{ {n}, {p, q}, {p, b, c}, {a, b, q}, {a, b, c} } k
Cuts per node 4 6 5 20 80 7
150
Computation is done bottom-up
The set of cuts of a node is a ‘cross product’ of the sets of cuts of its children.
Any cut that is of size greater than k is discarded.
(P. Pan et al, FPGA ’98; J. Cong et al, FPGA ’99)

20. Bitwise Simulation
Assign particular (or random) values at the primary inputs
Multiple simulation patterns are packed into 32- or 64-bit strings
Perform bitwise simulation at each node
Nodes are ordered in a topological order
Works well for AIG due to
The uniformity of AND-nodes
Speed of bitwise simulation
Topological ordering of memory used for simulation information 1 2 3 4 1 a b c d F 1 2 3 4 1 1 2 3 4 1 1 2 3 4 1 1 1 1

21. Boolean Satisfiability
Given a CNF formula (x), satisfiability problem is to prove that (x)  0, or to find a counter-example x’ such that (x’)  1
Why this problem arises?
If CNF were a canonical representation (like BDD), it would be trivial to answer this question.
But CNF is not canonical. Moreover, CNF can be very redundant, so that a large formula is, in fact, equivalent to 0.
Looking for a satisfying assignment can be similar to searching for a needle in the hay-stack.
The problem may be even harder, if there is no needle there!

22. Example (Deriving CNF)ab
(a + b + c)
(a + b + c’)
(a’ + b + c’)
(a + c + d)
(a’ + c + d)
(a’ + c + d’)
(b’ + c’ + d’)
(b’ + c’ + d) cd 00 01 11 10 1
Cube: bcd’
Clause: b’ + c’ + d

23. Example (SAT Solving) 1 2 3 4 5 6 7 8 (¬b + ¬c + ¬d) (a + b + c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d) a b b c c c d d d d d
Courtesy Karem Sakallah, University of Michigan

24. SAT Solver SAT solver types
CNF-based, circuit-based
Complete, incomplete
DPLL, saturation, etc.
A lot of complex ideas is used to build an efficient SAT solver
Two literal clause watching
Conflict analysis with clause recording
Non-chronological backtracking
Variable ordering heuristics
Random restarts, etc
Applications in EDA
Verification
Equivalence checking
Model checking
Synthesis
Circuit restructuring
Decomposition
False path analysis
Routing, scheduling, etc
MiniSAT is a popular SAT solver (
Efficient (won many competitions)
Simple (600 lines of code)
Easy to modify and extend
Integrated into ABC

25. And-Inverter Graphs Definition and examples
Several simple tricks that make AIGs work
Sequential AIGs
Unifying representation
A typical synthesis application: AIG rewriting

26. AIG Definition and Examples
AIG is a Boolean network composed of two-input ANDs and inverters.
cdab 00 01 11 10 1
F(a,b,c,d) = ab + d(ac’+bc) b c a d
6 nodes
4 levels
F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d)
cdab 00 01 11 10 1 a c b d
7 nodes
3 levels

27. Three Simple Tricks Structural hashing Complemented edges
Makes sure AIG is always stored in a compact form
Is applied during AIG construction
Propagates constants
Ensures each node is structurally unique
Complemented edges
Represents inverters as attributes on the edges
Leads to fast, uniform manipulation
Does not use memory for inverters
Leads to efficient structural hashing
Memory allocation
Uses fixed amount of memory for each node
Can be done by a simple custom memory manager
Even dynamic fanout manipulation is supported!
Allocates memory for nodes in a topological order
Optimized for traversal in the same topological order
Small static memory footprint for many applications a b c d
Without hashing a b c d
With hashing

28. Sequential AIGs
Sequential networks have memory elements in addition to logic nodes
Memory elements are modeled as D-flip-flops
Initial state {0,1,x} is assumed to be given
Several ways of representing sequential AIGs
Additional PIs and POs in the combinational AIG
Additional register nodes with sequential structural hashing
Sequential synthesis (in particular, retiming) annotates registers with additional information
Takes into account register type and its clock domain

29. AIG: A Unifying Representation
An underlying data structure for various computations
Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager
A unifying representation for the whole flow
Synthesis, mapping, verification use the same data-structure
Allows multiple structures to be stored and used for mapping
The main functional representation in ABC
A foundation of logic synthesis

30. AIG Rewriting
AIG rewriting aims at minimizing the number of AIG nodes without increasing the number of AIG levels
Pre-computing AIG subgraphs
Consider function f = abc
Rewriting AIG subgraphs
Rewriting node A a b c A
Subgraph 1 b c a A
Subgraph 2 a b c
Subgraph 1 b c a
Subgraph 2 a c b
Subgraph 3 
Rewriting node B b c a B
Subgraph 2 a b c B
Subgraph 1  a b c
In both cases 1 node is saved

31. Design Flow Property Checking System Specification
Verification
Equivalence checking
RTL
Logic synthesis
Technology mapping
Physical synthesis
Manufacturing

32. AIG-Based Solutions
These AIG-based solutions are part of a typical design flow
Synthesis
Mapping
Verification

33. AIG-Based Solutions (Synthesis)
Restructures AIG or logic network by the following transforms
Algebraic balancing
Rewriting/refactoring/redecomposition
Resubstitution
Minimization with don't-cares, etc
Synthesis D1 D2 D3 D4
Synthesis with choices D1
HAIG D4 D2 D3

34. AIG-Based Solutions (Mapping)
Input: A Boolean network (And-Inverter Graph)
Output: A netlist of K-LUTs implementing AIG and optimizing some cost function a b c d f e a b c d e f
Technology
Mapping
The subject graph
The mapped netlist

35. AIG-Based Solutions (Verification)
Property checking p
Property checking
Takes design and property and makes a miter (AIG)
Equivalence checking
Takes two designs and makes a miter (AIG)
The goal is to transform AIG until the output is proved constant 0 D2 D1
Equivalence checking

36. Summary Started with the fundamentals Introduced logic synthesis
Boolean variable, function, representation, etc
Introduced logic synthesis
Transforming functionality into structure
Described logic synthesis computations
Traversal, windowing, simulation, etc
Reviewed And-Inverter Graphs (AIGs)
Explained why they are useful
Discussed practical AIG-based solutions
Synthesis, mapping, verification