1. Complex Programmable Logic Devices
EE 365
Complex Programmable Logic Devices

2. PLDs
16V8 (20 Pins)
can have 16 inputs (max) and/or 8 outputs (marcrocells)
has 32 inputs to each of the AND gates (product terms)
22V10 (24 pins)
can have 22 inputs and/or 10 outputs (max)
has 44 inputs to each of the AND gates
How about a “128V64” for larger applications?
It will be slower and will more wasted silicon space
Solution? Use CPLDs

3. GAL16V8 (review seq_1.ppt) The OR gates
Each output is programmable as combinational or registered
Also has programmable output polarity
XOR gates to
make inverting or
non-inverting buffer
And Plane

4. A General CPLD structure
A collection of PLDs on a single chip with
Programmble interconnects

5. Let’s takes a look at this
Who makes the CPLDs?
Manufacturer CPLD Products URL
Altera MAX 5000, 7000 &
Altmel ATF & ATV
Cypress FLASH370, Ultra
Lattice ispLSI 1000 to
Philips XPLA
Vantis MACH 1 to
Xilinx XC
Let’s takes a look at this

6. The Xilinx 9500-series CPLD
The internal PLDs are called Configurable Functional Blocks
(FBs or CFBs)
Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”)
Each CLPD is packaged in a plastic-leaded chip carrier (PLCC)
The number of I/O pins are much less than the total number of
Macrocells in family of devices

7. Xinlinx CPLDs

8. Architecture of Xilinx 9500-family CPLD
36 Signal pins
18 outputs
Global Clock
Global set/reset
18 Output
enable signals
Global 3 state control

9. Architecture of Xilinx FB
Most CLPDs have fewer AND terms per macrocell
XC9500 has 5 whereas 16V8 has 8 and 22V10 has 8-16
But…each macrocell can use unused ANDs froms its
neigboring macrocells using the “product-term-allocators”

10. XC9500 Product
term allocator and
macrocell

11. ISP

13. XC9500 I/O Block

16. XC4000E I/O Block