1. Prof. Nitin Ahire XIE, Mahim
I/O Interfacing with 8085
Prof. Nitin Ahire
XIE, Mahim
Prof. Nitin Ahire

2. fundamentals of I/O devices
I/p Port
I/P PORT
Buffer
D0-D7
Data from Keyboard
D0-D7
Enable
Prof. Nitin Ahire

3. fundamentals of I/O devices
O/p Port
O/P PORT
latch
D0-D7
Data to Display
D0-D7
Enable
Prof. Nitin Ahire

4. I/O interfacing techniques
Up support I/O interface tech.
It partitions memory from I/O, via software
instruction like IN add, OUT add
When these instructions decoded by the processor it generate appropriate control signals IO/M^
In 8085 it is possible to connect 256 I/O ports and 64Kb memory
Prof. Nitin Ahire

5. I/O interfacing techniques
I/O devices can be interfaced in two ways
I/O mapped I/O
Memory mapped I/O
Prof. Nitin Ahire

6. I/O interfacing techniques
Memory mapped I/O
In this device add is 16 bit ( A0-A15)
MEMR^ and MEMW^ control signals are used
Instructions are LDA add, STA Add, MOV A,M
Data trans. Bet reg and I/O devices
No. of I/O devices interface= 65536
( Theoretically)
I/O mapped I/P
In this device add is 8 bit (A0-A7)
IOR^ and IOW^ control signals are used
Instruction are IN Add, OUT Add
Data trans. Bet acc and I/O devices
No. of I/O devices interface= 256 only
Prof. Nitin Ahire

7. I/O device selection for add (80h)
Data bus
Buffer Or
latch A0
Decoder A1
Data bus
To I/O device A2
IO/M^
NOT OR A3
G1^
RD^/WR^
Enable A4
IOR^/IOW^ A5 OR
G2^ OR A6 Y0 G A7
Prof. Nitin Ahire

8. IN 80h ( here 80h is the address of i/p switches)
A15/A7
A14/A6
A13/A5
A12/A4
A11/A3
A10/A2
A9/A1
A8/A0 1
Prof. Nitin Ahire

9. I/O device selection for add (80h)
I/P switches
S0-S7
Data bus
Buffer Or
latch A0
3:8
Decoder
Select
lines A1
Data transfer to Accumulator A2
IO/M^
NOT OR A3
G1^
RD^/WR^
Enable
IOR^/IOW^ A4
G2^ A5 OR OR A6 Y0 G A7
Prof. Nitin Ahire

10. I/O device selection for add (81h)
0/P Display devices
Data bus
Buffer Or
latch A0
3:8
Decoder
Select
lines A1
Data transfer to Accumulator A2
IO/M^
NOT OR A3
G1^
RD^/WR^
Enable
IOR^/IOW^ A4
G2^ A5 OR OR A6 Y1 G A7
Prof. Nitin Ahire