2. Access the Instruction from MemoryPC
Address
Next PC Logic
Instruction
Memory
Simplified Overview
Instruction
Access the Instruction from Memory

3. Access the Data from RegistersPC
Address
Next PC Logic
Instruction
Memory
Simplified Overview
Instruction
Register
File
Access the Data from Registers

4. Perform the InstructionPC
Address
Next PC Logic
Instruction
Memory
Simplified Overview
Instruction
Register
File
ALU
Perform the Instruction

5. Write the Result PC Next PC Logic Address Instruction Memory
Simplified Overview
Instruction
Addr
Register
File
Data
Memory
ALU
Data
Out
Data In
Write the Result

6. PC Next PC Logic Address Instruction Memory Simplified Overview
Register
File
Data
Memory
ALU
Data
Out
Data In
Timing Assumption

7. Basic Instruction Fetch
PC PC
Adder 4 PC
Address
M[PC]
Instruction
Instruction Memory

8. MIPS - Lite
Consider the following instructions for implementation
INSTRUCTION OP FUNCT
R type
add
subtract
AND OR
set on less than 0 42
load word na
store word na
branch equal 4 na

9. R type Arithmetic Logic Instructions
add rd, rs, rt
R op rs rt rd shamt funct
All R type Instructions
Read two registers addressed by rs and rt
Write one register addressed by rd
R[rs] + R[rt] R[rd] for add

10. Register File R e a d r e g i s t e r n u m b e r 1 R e g i s t e r RR e g i s t e r 1 M u R e a d d a t a 1 x R e g i s t e r n – 1 R e g i s t e r n R e a d r e g i s t e r n u m b e r 2 M u R e a d d a t a 2 x

11. Register File W r i t e C R e g i s t e r 1 D n - t o - 1 C R e g i s t e r n u m b e r d e c o d e r R e g i s t e r 1 D n – 1 n C R e g i s t e r n – 1 D C R e g i s t e r n R e g i s t e r d a t a D
Note: we still use the real clock to determine when to write

12. n to 1 Decoder RA4 RA3 RA2 RA1 RA0 Multiplexor ••• 31 1 R0i R1i Dri +
OOOOO
OOOO
••• 1 31
R0i
R1i
Dri + • •
R31i

13. Register File R e a d r e g i s t e r n u m b e r 1 R e a d d a t a 12 R e g i s t e r f i l e W r i t e r e g i s t e r R e a d d a t a 2 W r i t e d a t a W r i t e

14. R type Arithmetic Logic Instructions
add rd, rs, rt
R op rs rt rd shamt funct
All R type Instructions
Read two registers addressed by rs and rt
Write one register addressed by rd
R[rs] + R[rt] R[rd] for add

15. Dataflow for R – type Arithmetic – Logical Instructions add rd, rs, rt
Instruction R[rs] + R[rt] R[rd] A L U c o n t r l R e g W i s a d 1 2 u D m b . Z 5 rs rt rd 3
ALU is Combinational Logic

16. PC Next PC Logic Address Instruction Memory Simplified Overview
Register
File
Data
Memory
ALU
Data
Out
Data In
Timing Assumption

17. Load Word & Store Word ( I – type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs)
op rs rt imm16
lw # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
sw # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]

18. M[ R[rs] + sign_ext(imm16) ] R[rt]
load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
Registers
Data Memory rs rt R1 R2 Rw Dw
Dr1
Dr2
ALU
Addr Dr Dw
imm16
sign
ext 16 32

19. R[rt] M[ R[rs] + sign_ext(imm16) ]
store word
R[rt] M[ R[rs] + sign_ext(imm16) ]
Registers
Data Memory rs rt R1 R2 Rw Dw
Dr1
Dr2
ALU
Addr Dr Dw
imm16
sign
ext 16 32

21. beq rs, rt, imm I -type
op rs rt imm16
Zero =1 iff rs - rt = 0
If Zero = 1
SUM (ShLt2[Sign_Ext(imm16)] + PC+4) PC
If Zero = 0
PC PC
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC

22. Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4]
Ex: imm16 is

23. Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4]
Ex: imm16 is
Sign_Ext(imm16) is

24. Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4]
Ex: imm16 is
Sign_Ext(imm16) is
ShLt2[Sign_Ext(imm16)] is

25. Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4]
Zero =1 iff rs - rt = PC
PC+4
Sum to PC
ALU
Shift
Left 2
branch equal
imm16
sign
ext 16 32

26. Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4]
Zero =1 iff rs - rt = PC
PC+4
Sum to PC
ALU
branch equal
Shift
Left 2
Registers
ALU op
Zero rs rt R1 R2 Rw Dw
Dr1
Dr2
ALU
imm16
sign
ext 16 32

27. Dataflow Review Fig 4.11 page 3152 4 M u x A L U o p e r a i n 3 R g W m d P C S c s l Z D y P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l M x g W S h f