1. Topics covered so far... What is architecture? 4 design principles
Organization? Implementation? NO
It ‘s an interface between hardware and software
An abstraction presented to the programmer
4 design principles
Design for the common case
Smaller is faster
KISS principle / simplicity favors regularity
Good design demands compromise
Little endian vs. Big endian
Instruction classes
Why divide into classes?
How do I extend the current encoding to incorporate a new instruction? (eg. Where should the immediate go? Which one should be the src register? The destination register?
Pseudoinstructions
Use only actual MIPS instructions while expanding
Eg. sqr rdest, rsrc
2/24/2019
Ashish Sabharwal

2. Topics covered so far… (cont’d)
Procedure calls
Calling conventions Which ones are caller saved ? Callee saved ?
Stack usage subu $sp, $sp, 8 sw $t1, 4($sp) sw $t2, 0($sp) ….. lw $t1, 4($sp) lw $t2, 0($sp) addu $sp, $sp, 8
RISC vs. CISC
Why was CISC good / bad ?
Why is RISC good / bad ?
Performance metrics
What does CPI represent ?
How is speedup calculated ?
Why is execution time a good measure?
Why was MIPS popular ? Is it a good metric ?
While calculating, it’s a good idea to start with 100 instructions instead of working with fractions of 1.
2/24/2019
Ashish Sabharwal

3. Topics covered so far… (cont’d)
Implementation techniques
Datapath
Control
Know what signals are needed and why
Can you roughly draw some datapath+control ? (though you will be given a figure in exam, if required)
Single cycle vs. multicycle implementation
Advantages of multicycle
Can you go thru a multicycle implementation cycle by cycle ?
Two techniques for actual implementation
Finite state machines (direct hardware design)
Microprogramming
Know the distinction between these two options clearly
Advantages / disadvantages earlier ?
Advantages / disadvantages now ?
2/24/2019
Ashish Sabharwal

4. Performance: something to remember
An improved program may not always have a lower CPI, but it will definitely have a lower execution time.
(Similar to problem 7 on assignment 4) ALU ops 40% 1 cycle Load/stores 20% 2 cycles Branches 40% 3 cycles Original CPI = (40x1 + 20x2 + 40x3) / 100 = 2.0 Original execution time (assuming 100 instructions) = (40x1 + 20x2 + 40x3) = 200 cycles
…. the new machine executes 1/2 less branches ….. New CPI = (40x1 + 20x2 + 20x3) / 80 = execution time = (40x1 + 20x2 + 20x3) = 140 cycles
…. the new machine executes 1/2 less ALU ops ….. New CPI = (20x1 + 20x2 + 40x3) / 80 = execution time = (20x1 + 20x2 + 40x3) = 180 cycles
2/24/2019
Ashish Sabharwal

5. Addition to multicycle implementation
Example - Add the following instruction to the multicycle implementation merge rdest, rlow, rhigh Semantics: Take the low order 16 bits of rlow, and merge them with the high order 16 bits of rhigh to form a 32 bit “merged” word. rlow = a31a30….a16a15……..a1a0 rhigh = b31b30….b16b15……..b1b0 rdest = b31b30….b16a15……..a1a0
Highlight used datapath (use your own judgement to not highlight things that do not relate directly to this instruction, such as PC increment)
If required, add new components and label them
If a mux widens, show that change clearly
If width of a wire changes, mark the change
It’s a good idea to bring 1 or 2 color pens/pencils to exam
2/24/2019
Ashish Sabharwal