1. Chapter 8 MOS Memory and Storage Circuits
Microelectronic Circuit Design
Richard C. Jaeger Travis N. Blalock
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

2. Microelectronic Circuit Design
Chapter Goals
Overall memory chip organization
Static memory circuits using the six-transistor cell
Dynamic memory circuits
Sense amplifier circuits used to read from memory cells
Learn about row and address decoders
Implementation of CPU registers via flip-flops
Pass transistor logic
Read Only Memory
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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3. Microelectronic Circuit Design
Random Access Memory
Random Access Memory (RAM) refers to memory in a digital system that has both read and write capabilities
Static RAM (SRAM) are able to store there information as long as power is applied, and they will not lose their data during a read cycle
Dynamic RAM (DRAM) uses a capacitor to temporarily store data which must be refreshed periodically to prevent information loss, and the data is lost in most DRAMs during the read cycle
SRAM takes approximately four times more Silicon area as DRAM
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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4. Microelectronic Circuit Design
A 256-MByte Memory Chip
The figure shows the block structure of a 256-Mb memory
There are sets of column and row decoders that are used for memory array selection
The column decoder splits the memory into upper and lower halves
The row decoder and wordline driver bisects each 32-Mb subarray
Note that the basic building block for this memory if a 128Kb cell
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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5. Microelectronic Circuit Design
A 256-MByte Memory Chip
The memory block diagram contains 2M+N storage locations
When a bit has been selected the set of sense amplifiers are used to read/write to the memory location
Horizontal rows are referred to as wordlines where the vertical lines are called bitlines
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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6. Microelectronic Circuit Design
Static Memory Cells
Inverters configured as shown in the above figure form the basic static storage building block
These cross-coupled inverters are often referred to as a latch
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

7. Static Memory Cells VTC
The previous latch has only two stable states termed bistable
However, it is possible for it to enter an unstable equilibrium point where slight changes in the voltage could give erroneous data
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

8. Microelectronic Circuit Design
The 6-T Cell
With the addition of two control transistors it is possible to create the 6-T cell which has both the true and complemented values
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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9. The Read Operation of a 6-T Cell
Initial state of the 6-T cell storing a 0 with the bitlines’ initial conditions assumed to VDD/2
Conditions after the WL transistors have been turned on
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

10. The Read Operation of a 6-T Cell
Final read state condition of the 6-T cell
Waveforms of the 6-T cell read operation
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

11. The Read Operation of a 6-T Cell
Reading a 6-T cell that is storing a “1” follows the same concept as before, except for the sources and drains of the WL transistors are switches
Note that the delay is approximately 20ns for this particular cell
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

12. The Write Operation of a 6-T Cell
It can be seen that not much happens while writing a “0” to a cell that is already storing a “0”
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

13. The Write Operation of a 6-T Cell
While writing a “0” to a cell that is storing a “1”, the bitlines must be able to overpower the output drive of the latch inverters to force it to store the new condition
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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14. Microelectronic Circuit Design
Dynamic Memory Cells
The 1-T cell uses a capacitor for its storage element (either a presence or absence of a charge)
Due to leakage currents of MA, the data will eventually become corrupt, hence it needs to be refreshed
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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15. Data Storage in a 1-T Cell
Storing a 0
Storing a 1
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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16. Data Storage in a 1-T Cell
Notice that the voltage stored on the storage capacitor on the previous slide does not reach VDD
It instead is determined by the following:
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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17. Data Storage in a 1-T Cell
To read a DRAM cell, the bitline is precharged to either VDD or VDD/2, and then MA is turned on
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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18. Data Storage in a 1-T Cell
The charge stored on CC will be shared with CBL through the process of charge sharing, where the read voltage varies slightly
Where CBL>> CC and the charging time constant is:
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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19. The Four-Transistor (4-T) Cell
Since the 6-T SRAM provides a large signal current drive to the sense amplifier, they generally have shorter access times compared to the DRAM
The 4-T DRAM cell is an alternative that increases access time, and automatically refreshes itself
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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20. Reading and Writing to the 4-T DRAM Cell
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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21. Microelectronic Circuit Design
Sense Amplifiers
Sense amplifiers are used to detect small currents that flow through the access transistors or the small voltage differences that occur during charge sharing
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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22. A Sense Amplifier for the 6-T Cell
MPC is the precharge transistor whose main purpose is to force the latch to operate at the unstable point previously mentioned
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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23. Sense Amplifier Example
For the figure on the previous slide, find the currents in the latch transistors when MPC is turned on with the following given:
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

24. Sense Amplifier Example
Since the output voltage should equal on both sides of the latch when MPC is on, it is known that VGS = VDS for the latch NMOS devices and VSG = VSD for the latch PMOS devices. Therefore these transistors are saturated
Due to the symmetry of the situation, the drain currents are equal giving the following:
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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25. Sense Amplifier Example
The drain currents are then found by (PMOS and NMOS drain currents are equal):
And the power dissipation is found by:
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

26. Sense Amplifier for the 1-T Cell
The same sense amplifier used in the 6-T cell can be used for the 1-T cell in manner shown in the figure
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

27. Sense Amplifier for the 1-T Cell
The sense amplifier works the same as it did for the 6-T cell, but takes longer to reach steady state after precharge
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

28. The Boosted Wordline Circuit
Obviously it is desired to have a fast access in many DRAM application, so by driving the wordline to a higher voltage (referred to as a boosted wordline), 5V instead of 3V, it is possible to increase the amount of current supplied to the storage capacitors
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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29. Clocked CMOS Sense Amplifiers
The sense amplifier can definitely be a major source of power dissipation, but be using a clocking scheme, it is possible to reduce the power dissipated
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

30. Clocked CMOS Sense Amplifiers
Clocking the previous circuit in the manner shown in the figure will eliminate static currents in the latch during the precharge state, and only transient currents will appear
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

31. Microelectronic Circuit Design
Address Decoders
The following figures are examples of commonly used decoders for row and column address decoding
NMOS NAND Decoder
NMOS NOR Decoder
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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32. Microelectronic Circuit Design
Address Decoders
Complete 3-bit domino CMOS NAND decoder
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

33. Microelectronic Circuit Design
Address Decoders
3-bit column data selector using pass-transistor logic
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
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34. Read-Only Memory (ROM)
ROM is often needed in digital systems such as:
Holding the instruction set for a microprocessor
Firmware
Calculator plug-in modules
Cartridge style video games
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

35. Read-Only Memory (ROM)
The basic structure of the NMOS static ROM is shown in the figure
The existence of a NMOS means a “0” is stored at that address otherwise a “1” is stored
The major downfall to this particular circuit is that it dissipates a lot of power
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

36. Read-Only Memory (ROM)
The domino CMOS ROM is one technique used to lower the amount of power dissipation
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

37. Read-Only Memory (ROM)
Another ROM option is the NAND array ROM which can be directly used with a NAND decoder
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

38. Read-Only Memory (ROM)
The main problem with these previous ROMs is that they must be designed at the mask level, meaning that it was not a versatile product.
To solve this problem, the programmable ROM (PROM) was introduced
The standard PROM cannot be erased, so the erasable ROM (EPROM), and later, electrically erasable ROM (EEPROM) were introduced
High density flash memories allow for selective electrical erasure and reprogramming of memory cells
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

39. Microelectronic Circuit Design
RS Flip-Flop
The reset-set (RS) flip-flop can be easily realized by using either two cross-coupled NOR or NAND gates
The RSFF has the following truth tables
NOR RSFF
NAND RSFF R S Q 1 R S Q 1
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

40. Microelectronic Circuit Design
RS Flip-Flop
NOR RSFF
NAND RSFF
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

41. Microelectronic Circuit Design
RS Flip-Flop
Simplified RS flip-flop
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

42. Microelectronic Circuit Design
D-Latch using T-Gates
A very important circuit of digital systems is the D-Latch which is used for a D flip-flop
Whenever C (clock) goes high in the below D-Latch, whatever is on D is passed through to Q
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

43. Master-Slave D Flip-Flop
By using series D-Latches that latch the data on opposite clock phases, a D flip-flop can be realized as shown in the figure
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill

44. Microelectronic Circuit Design
End of Chapter 8
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill