1. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation Contact Reinier A. van Mourik, MSc PhD Researcher Spintronics Devices IBM / Eindhoven University of Technology IBM Almaden Research Center 650 Harry Rd San Jose, CA 95120 USA Tel+1 408 927 2501 Fax+1 408 927 2510 Mobile+1 408 821 4559 rvmourik@us.ibm.com

2. © 2009 IBM Corporation Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation Reliability of Signal Propagation in Magnetostatically Coupled Arrays of Magnetic Nanoelements Reinier van Mourik 1,2, Li Gao 1, Brian Hughes 1, Charles Rettner 1, Bert Koopmans 2, Stuart Parkin 1 1. IBM Almaden Research Center, San Jose, CA 2. Eindhoven University of Technology, Eindhoven, the Netherlands

3. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 1. Introduction Nanomagnetic logic - principle Energy-efficient Non-volatile Fast Radiation resistant Majority gate A BD C M A B C D M Majority gate is programmable NAND/NOR gate Full logic set output read

4. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 1. Introduction Outline Experiment and simulation: inherent unreliability Alternative for conventional NML: Domain wall clocking

5. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Experiment setup fabrication measurement Artificial input biases first dot according to reset direction ~70Oe d514 MFM shows state of each dot The RH curve of the MTJ shows output of device

6. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Single device: shot-to-shot results Output MTJ state alternates accordingly when alternating input direction. input output

7. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Many devices: device-to-device results Success/error is highly reproducible, thus inherent in device. 68/158 (43%) of devices contain errors repeat clocking cycle, input +x clocking cycle, input +x clocking cycle, input -x 116/123 (94%) of devices evolve to exact same state 66/79 (84%) of devices evolve to exact inverse state

8. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Error rate in signal propagation - simulations Device-to-device error rate tends to 50% as length increases Last NM evolves before signal reaches it Errors are caused by last magnet evolving early.

9. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking Domain wall clocking - principle Fringing field from domain wall in perpendicularly magnetized material can reset nanomagnets.

10. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking DW clocking – experimental setup PMA nanowire 60-180nm wide Domain wall injection line Hall bar nanodots Py 60x90x20nm AMR read hall bar read DW 1. inject DW 2. propagate DW by H field 3. read resistance change in AMR and Hall bar

11. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking DW clocking - results Prepare device in incorrect state Pass DW underneath End in correct state DW clocking demonstrated in 1- and 2-magnet devices

12. IBM Research Nanomagnetic Logic | Mar 18 2013 | IBM/TUe © 2013 IBM Corporation Conclusion Nanomagnetic Logic is magnetic alternative to CMOS logic Analysis done of reliability of NML devices with integrated output Errors are reproducible per device and tend to 50% among devices. Domain Wall clocking is demonstrated as alternative clocking scheme slides & contact: http://tinyurl.com/RvM-IBMhttp://tinyurl.com/RvM-IBM