1. Digital Down Conversion
Introduction to available Hardware
By: S.M. Amin Motahari

2. What we will see: Modern Communication Structures DDC Chips:
TI’s Chips
AD’s Chips
GC5016 Digital Up/Down Converter
Innovative Integration Boards

3. WiMAX Wireless Infrastructure
GC5016 Can Be Placed Here

4. WCDMA & CDMA2000 4/8-Carrier, Receive Diversity RX/TX
GC5016 Can Be Placed Here

5. Texas Instruments DDCs
Part Number  
Clock Rate (max) (MSPS)  
Conversion Method  
Wideband Channels
Input Resolution (max) (Bits)  
Output Resolution (max) (Bits)  
SFDR (dB)  
Power/ Channel (max) (mW)  
Automatic Gain Control  
Pin/Package  
GC1012B
100
Down 1 12 16 75
850
120QFP
GC4016 2 24
115
160BGA
GC4116
105 Up 22
150
GC5016
160
Down, Up 4
250
Yes
252BGA
GC5018 8
305BGA
GC5316
125 18
225
388BGA
GC5318

6. Analog Devices DDCs

7. GC5016 Down Conversion Features
Input Rates to 160-MSPS for Four Channels, 320-MSPS for Two Channels in Double Rate Mode
Four Wideband Down-Conversion Channels support UMTS Standards
SFDR 115-dB
FIR Filter Block Consists of 16 Cells Providing Up to 256 Taps Per Channel
64 Parallel Input Bits and 64 Parallel Output Bits Provide Flexible I/O Options
Many Multiplex Output Options

8. GC5016 Up-Conversion Features
Output Rates to 160-MSPS for Four Channels, 320-MSPS for Two Channels
Four Up-Conversion Channels Support UMTS Standards
FIR Filter Block Consists of 16 Cells Providing up to 256 Taps Per Channel
64 Parallel Input Bits and 64 Parallel Output Bits Provide Flexible I/O Options
Multiple Real and Complex Outputs
Outputs Can Be Independent, Summed Into Two or One Output(s), and Optionally Merged With Multiple GC5016 Chips

9. GC5016 Applications
Cellular Base Transceiver Station Transmit and Receive Channels − WCDMA − CDMA2000
Radar
General Filtering
Test and Measurement

10. Functional Block Diagram D/C mode
NCO
RINF I
Dual CIC AI
RSEL
PFIR
AGC
ROUTF Q
Cross connect for Double rate
RINF I
Dual CIC BI
RSEL
PFIR
AGC
ROUTF Q
NCO X2

11. Receive Input Formatter (RINF)
Half Rate
Complex Input, one signal per input port
Full Rate
Real Input, one signal per input port
Complex Input, one signal per two input ports (I and Q)
Double rate
Real Input, one signal per two input ports (even and odd)
Complex Input, one signal per four input ports (Ieven, Qeven, Iodd, Qodd)
Full Rate means the sample input rate is equal to the GC5016 clock rate.

12. Receive Input Formatter (RINF)
Diagnostic Selection
RINF
Counter
Zero
Constant
Pseudo-random Noise
Tone

13. Receive Input Selection (RSEL)
BUS AI I Q BI CI DI

14. Mixer RSEL MIX Sel 16 18 RSEL MIX Sel 16 18 COS(NCO) 20 REAL 21bits
AI BI CI DI
AQ BQ CQ DQ
RSEL
MIX Sel 16 18
RSEL
MIX Sel 16 18
COS(NCO) 20
REAL 21bits
IMAG 21bits
SIN(NCO) 20 18 18

15. Numerically Controlled Osc. (NCO)
Phase Offset
Dither Generator
7Bits
48Bits
16Bits
Sin/Cos Out 20Bits
Freq word 48Bits
Sine/Cosine Lookup Table 23 18

16. CIC Decimate Filter It’s a 5 stage decimating filter.
Each CIC channel contains two CIC filters (one for I and one for Q)
Contains: scaling integration rate change comb filtering output scaling

17. Programmable Finite Impulse Response Filter (PFIR)
A forward 16x18-bit (16 words with 18-bit width) tap delay RAM
A backward 16 x 18-bit tap delay RAM (used for symmetric filters)
Control
A pre-adder with 18-bit output
A 16x16-bit filter coefficient RAM

18. Power Meter
The power meter integrates the power over a number of PFIR output samples
The power meter squares the I or Q top 12 bits of the data, keeps the top 17 bits of the result, and integrates it for up to words.
Handshaking is provided to let the user know when data is ready
The power meter output is read as a 32bit result over the Microprocessor port.

19. Automatic Gain Control (AGC)
The basic operation of the circuit is to multiply the 20-bit input data from the PFIR by a 19-bit gain word that represents a gain or attenuation in the range of 0 to 128
M : 7 Bits
L : 12 Bits
19 Bits Gain Word
Adjust in .002dB Steps
42 dB Boost in .33db Steps

20. Receiver Output Interface (ROUTF)
Parallel IQ or real output − in this mode, there is one output per Frame Strobe and each channel is output on its own pins.
Interleaved IQ − in this mode, the Frame Strobe identifies the start of I of the interleaved IQ output. In this format, I is output first, followed by Q Each channel is output on its own pins.
Time Division Multiplexed IQ − in this mode, all of the DDC channels are output from the D output port, The Frame Strobe identifies the start of each TDM frame. The output order in 4 channel mode is: ID, QD, IC, QC, IB, QB, IA, QA. The output order in 2 channel split IQ mode is: QD, IC, QB, IA

21. Control Interface Control Interface Single Strobe Edge Based
Latch Based
Dual Strobe
Using C[15..0], A[4..0], CE, RD, and WR pins.
RD and WR pins are used as separate strobes

22. Innovative Integration Boards
Digital Receiver PMC/XMC Module
Features
Applications
. Four LTC2255, 14-bit, 125 MSPS converters · Four GC5016 Digital Receivers · Virtex-II Pro FPGA, 4 Million gates · PCI 64/66 with P4 port to host card · 16MB SDRAM plus 2MB RAM for FPGA · Low-jitter PLL clock source · Advanced SW and firmware demo programs · XMC - 10 Gbps full duplex 
· Software Defined Radio (SDR) · Signal Identification · Electronic Warfare · Advanced RADAR · Hardware Testing · Telecom IP development

23. Block Diagram

24. X5-400M PCI Express , XMC Module
Features
Applications
· Two 400 MSPS, 14-bit A/D channels · Two 400 MSPS, 14-bit DAC channels · Xilinx Virtex5, LX110T FPGA (SX95T coming) · 1GB DDR2 DRAM · 4MB QDR-II SRAM · 8 Rocket IO private links, 2.5 Gbps each · >1 GB/s, 8-lane PCI Express Host Interface · Power Management features · PCI Express (VITA 42.3)
· Wireless Receiver and Transmitter · WLAN, WCDMA, WiMAX front end RADAR · Electronic Warfare · High Speed Data Recording and Playback · High speed servo controls · IP development

25. Resources GC 5016 Quad Digital Up/Down Converter Datasheet
GC5016 GC Studio User's Guide
Texas Instruments Wireless infrastructure Diagrams:
Innovation Integration Products :
Analog Devices AppNotes:
AN-807 Multicarrier WCDMA Feasibility
AN-808 Multicarrier CDMA2000 Feasibility
AN-851 A WiMax Double Downconversion IF Sampling Receiver Design

26. Any Comments and/or Questions
END