1. CNET 315 Microprocessor & Assembly Language
Phiros Mansur Nalakath
Course Coordinator
College of Computer Science & Information Systems, Jazan University, KSA

2. Interrupts in 8086 Microprocessor
Chapter - 5
Interrupts in Microprocessor

3. Interrupt
Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor.
The microprocessor responds to the interrupt with an ISR (Interrupt Service Routine).
ISR is a short program to instruct the microprocessor on how to handle the interrupt.

4. Types of Interrupts in 8086

5. Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through the specified pins NMI or INTR to the microprocessor.
NMI is a Non-Maskable Interrupt and INTR is a maskable interrupt having lower priority.
INTA called Interrupt Acknowledge.

6. Hardware Interrupts... NMI Single non-maskable interrupt pin (NMI)
Higher priority than INTR interrupt
Type 2 interrupt
INTR
INTR is a maskable interrupt
INTR interrupt is activated by an I/O port.

7. Software Interrupts
Some instructions in the program can create interrupts like,
INT instruction with type number
There are 256 interrupt types under this group.

8. Interrupt Execution steps
Flag register value is pushed to the stack.
CS value and IP value of the return address are pushed on to the stack.
IP is loaded from the contents of the word location ‘Type number’ × 4
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0

9. INTERRUPT VECTOR TABLE (IVT)

10. 8086 INTERRUPT TYPES TYPE 0 TO TYPE 4 INTERRUPTS-
256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS
TYPE 0 TO TYPE 4 INTERRUPTS-
These are used for fixed operations and
hence called as dedicated interrupts
TYPE 5 TO TYPE 31 INTERRUPTS
Not used by 8086,reserved for higher processors like etc
TYPE 32 TO 255 INTERRUPTS
Available for user, called user defined interrupts
These can be h/w interrupts and activated through INTR line or can be s/w interrupts.

11. Interrupt Types
TYPE 0 interrupt represents division by zero situation.
QUOTIENT IS LARGE CANT BE FIT IN AL/AX OR DIVIDE BY ZERO
TYPE 1 interrupt represents single-step execution during the debugging of a program.
USED FOR EXECUTING THE PROGRAM IN SINGLE STEP MODE BY
SETTING TRAP FLAG
TYPE 2 interrupt represents non-maskable NMI interrupt.
THIS INTERRUPT IS USED FOR EXECUTING ISR OF NMI PIN.
NMI CANT BE MASKED BY S/W
TYPE 3 interrupt represents break-point interrupt.
USED FOR PROVIDING BREAK POINTS IN THE PROGRAM
TYPE 4 interrupt represents overflow interrupt.
USED TO HANDLE ANY OVERFLOW ERROR AFTER
ARITHMETIC OPERATIONS

12. Interrupt Types Type 5: BOUND – Register contents out-of-bounds
Type 6: Invalid Opcode – Undefined opcode occurred in program
Type 7: Coprocessor not available – MSW indicates a coprocessor
Type 8: Double Fault – Two separate interrupts occur during the same instruction
Type 9: Coprocessor Segment Overrun – Coprocessor call operand exceeds FFFFH
Type 10: Invalid Task State Segment – TSS invalid (probably not initialized)
Type 11: Segment not present – Descriptor P bit indicates segment not present or invalid
Type 12: Stack Segment Overrun – Stack segment not present or exceeded
Type 13: General Protection – Protection violation in 286 (general protection fault)
Type 14: Page Fault – and above
Type 16: Coprocessor Error – ERROR΄ = ‘0’ (80386 and above)
Type 17: Alignment Check – Word/Doubleword data addressed at odd location (486 and above)
Type 18: Machine Check – Memory Management interrupt (Pentium and above)

13. PRIORITY OF INTERRUPTS
INTERRUPT TYPE
PRIORITY
INT0,INT3-INT 255,INTO
HIGHEST
NMI(INT2)
INTR
SINGLE STEP
LOWEST

14. Programmable Interrupt Controller 8259

15. 8259
The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system.
It accepts requests from the peripheral equipments.
Determines which of the incoming requests is of the highest priority.
Issues an interrupt to the CPU based on this determination

16. Cont’d
The PIC manages eight levels of requests and has built-in features for expandability to other PIC (up to 64 levels).
The priority modes can be changed or reconfigured dynamically at any time during main program operation

17. Block diagram of the 8259A Programmable Interrupt Controller

18. Three internal registers
input-signals
8259A
IRR
output-signal
IMR
ISR
IRR = Interrupt Request Register
IMR = Interrupt Mask Register
ISR = In-Service Register

19. Interrupt Request Register (IRR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (lRR) and the In- Service Register (lSR).
The IRR is used to indicate all the interrupt levels which are requesting service.

20. In-Service Register (ISR)
ISR is used to store all the interrupt levels which are currently being serviced

21. Priority Resolver
PR determines the priorities of the bits set in the lRR.
The highest priority is selected and strobed into the corresponding bit of the lSR during the INTA sequence.

22. Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to be masked.
The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt request lines of lower priority.

23. Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the PIC to the System Data Bus.
Control words and status information are transferred through the Data Bus Buffer.
D[7..0] are connected to the system bus and are used by the microprocessor to write or read the internal registers of the 8259.

24. Important Signals D0-D7 : Bidirectional data connections
IR0-IR7 : Interrupt request inputs
WR΄ : Write input strobe
RD΄ : Read input connects to the IORC΄signal
INT : Output, connects to μP INTR pin
INTA΄ : Input, connects to μP INTA΄ pin
A : Command word select
CS΄ : Chip select input
SP/EN΄ : Slave program/enable buffer pin
CAS0-CAS2 : Outputs from master to slave for cascading multiple 8259A chips

25. Questions… ?
Thank you…!