1. Jean-Francois Genat – Herve Grabas Mary Heinz – Eric Oberla
Sampling chip psTDC_02
psTDC_02 presentation
2/24/2019
Jean-Francois Genat – Herve Grabas Mary Heinz – Eric Oberla

2. Overall presentation : the principle
psTDC_02 presentation
2/24/2019
Overall presentation : the principle

3. Overall presentation : the chip architecture
psTDC_02 presentation
2/24/2019
Overall presentation : the chip architecture
Token read-out channels 1 & 2
Token read-out channels 3, 4 & 5
Control logic & Output bus
Test structures
Input signals
40MHz clock
Channels 1 & 2
Timing Generator
Channels 3, 4 & 5

4. The timing generator: principle
psTDC_02 presentation
2/24/2019
The timing generator: principle
256 cells
Fixed sampling window
To the channels
Variable sampling window
40MHz clock
DLL out monitoring

5. The timing generator Same architecture conserved
psTDC_02 presentation
2/24/2019
The timing generator
Same architecture conserved
Ajustable delay with two voltages
Fixed and variable window generation (improvement)

6. The channels: principle
psTDC_02 presentation
2/24/2019
The channels: principle
12 bits counter
Ring oscillator ck en
buffer
comparator rd wr
ramp
cap
(x 256)

7. The Channel Sampling window Buffer Comparator Counter - ADC
psTDC_02 presentation
2/24/2019
The Channel
Sampling window
Buffer
Comparator
Counter - ADC

8. The Sampling window More control logic Bigger input capacitance
psTDC_02 presentation
2/24/2019
The Sampling window
More control logic
Bigger input capacitance
Same bandwidth

9. The Buffer The Comparator Better input dynamic A bit slower
psTDC_02 presentation
2/24/2019
The Buffer
Better input dynamic
A bit slower
Use less current
The Comparator
Same spec
Use less current

10. Control signal Ramp generator Ring oscillator Trigger (improvement)
psTDC_02 presentation
2/24/2019
Control signal
Ramp generator
Ring oscillator
Trigger (improvement)
Selections unit for read out

11. The ramp generator Improved range and linearity
psTDC_02 presentation
2/24/2019
The ramp generator
Improved range and linearity
Hopefully fixed the in-chip coupling
Buffer per channel

12. The ring oscillator Added a fan-out: better clock distribution
psTDC_02 presentation
2/24/2019
The ring oscillator
Added a fan-out: better clock distribution

13. The Trigger Positive and negative pulse detection
psTDC_02 presentation
2/24/2019
The Trigger
Positive and negative pulse detection
Delay before triggering
Threshold level adjustable
Bypass possibility

14. The Readout Faster Better buffering
psTDC_02 presentation
2/24/2019
The Readout
Faster
Better buffering
Possible to select channels and block of 64 cells
Debugging possible via analog input and output