1. doc.: IEEE 802.15-<doc#>
<month year>
doc.: IEEE <doc#>
August 2004
Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs)
Submission Title: [High Rate Alt-PHY with shorter backward compatible mapping sequences]
Date Submitted: [27 Aug, 2004]
Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore]
Address: [21 Heng Mui Keng Terrace, Singapore ]
Voice: [ ] FAX: [ ]
Re: [Response to the call for proposal of IEEE b, Doc Number: b]
Abstract: [This presentation represents Institute for Infocomm Research (I2R)’s proposal for the P b PHY standard, emphasizing the need for a high rate alternative PHY for low cost system having excellent sensitivity and long battery life.]
Purpose: [Proposal to IEEE b Task Group]
Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
Francois Chin, Institute for Infocomm Research (I2R)
<author>, <company>

2. August 2004
Proposal
A set of shorter sequences for backward compatible Symbol-to-Chip mapping, with balanced BER performance using both direct sequence despreading and differential chip despreading, that can achieve various higher data rate
BPSK and Raised cosine pulse shape is used, with GHz PHY modulation scheme as option
Francois Chin, Institute for Infocomm Research (I2R)

3. Summary of Code Sets August 2004 Code Set A32 B16 C8 D8 E16
Description
32-chip
(15.4 original)
16-chip
(I2R proposed)
8-chip for DS Despreading
8-chip for Diff. Chip Despreading
(I2R proposed)
Orthogonal 16-DSSS
Sym-Chip mapping
Cyclic & Odd Bit Inversion
Orthogonal
Bit/sym 4 3
Bit/chip
0.125
0.25
0.5
0.375
Root Sequence (hex)
D9C3522E
3AFC B2 45
N.A.
DS Despreading (DSD)
Yes
Diffential Chip Despreading
(DCD) No
Francois Chin, Institute for Infocomm Research (I2R)

4. Features of Proposed Code Set
August 2004
Features of Proposed Code Set
Backward compatible:
Same sub-GHz modulation scheme – BPSK + Raised cosine pulse shape
Same 2.4GHz modulation scheme – OQPSK + Half-sine pulse shape
Same Symbol-to-Chip mapping, except with shorter code lengths (16/8 chip per symbol) than original length-32 code
16-chip sequences for 4-bit mapping, the mapping sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
8-chip sequences for 3 or 4-bit mapping, the mapping sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Proposed code sets have balanced BER performance using both direct sequence despreading and differential chip despreading
Francois Chin, Institute for Infocomm Research (I2R)

5. Adjacent Channel Spectra
August 2004
Adjacent Channel Spectra
Francois Chin, Institute for Infocomm Research (I2R)

6. Proposed Symbol-to-Chip Mapping (16-chip Code Set B16)
August 2004
Proposed Symbol-to-Chip Mapping (16-chip Code Set B16)
Decimal Value
Binary Symbol
Chip Value
0000
(Root - 3AFC) 1
1000 2
0100 3
1100 4
0010 5
1010 6
0110 7
1110 8
0001 9
1001 10
0101 11
1101 12
0011 13
1011 14
0111 15
1111
The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Francois Chin, Institute for Infocomm Research (I2R)

7. Other Root Sequences (16-chip Code Set B16)
August 2004
Other Root Sequences (16-chip Code Set B16)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: ….
Francois Chin, Institute for Infocomm Research (I2R)

8. August 2004
Proposed Symbol-to-Chip Mapping (8-chip Code Set C8 for DS Despreading)
DDecimal Symbol
Binary Symbol
Chip Values
(Root Sequence – B2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Francois Chin, Institute for Infocomm Research (I2R)

9. Other Root Sequences (8-chip C8 for DS Despreading only)
August 2004
Other Root Sequences (8-chip C8 for DS Despreading only)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:
Francois Chin, Institute for Infocomm Research (I2R)

10. Proposed Symbol-to-Chip Mapping (8-chip Code Set D8)
August 2004
Proposed Symbol-to-Chip Mapping (8-chip Code Set D8)
3-bit / symbol mapping
Decimal Value
Binary Symbol
Chip Value
000
(root – 45h) 1
100 2
010 3
110 4
001 5
101 6
011 7
111
The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Francois Chin, Institute for Infocomm Research (I2R)

11. Other Root Sequences (8-chip Code Set D8)
August 2004
Other Root Sequences (8-chip Code Set D8)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:
Francois Chin, Institute for Infocomm Research (I2R)

12. BER Performance Comparison (ALL)
August 2004
BER Performance Comparison (ALL)
Performance of proposed 16-chip and 8-chip code sets, in comparison with original PHY length-32 Symbol-to-Chip performance and Orthogonal DSSS sequences as in b-enhanced-oqpsk-modulation-with-orthogonal-dsss-sequences
Francois Chin, Institute for Infocomm Research (I2R)

13. BER Performance (DS Despreading)
August 2004
BER Performance (DS Despreading)
Performance comparison
DSSS > 32-chip > 16-chip > 8-chip (1/2 bit/chip) > 8-chip (3/8 bit/chip)
Francois Chin, Institute for Infocomm Research (I2R)

14. BER Performance (DC Despreading)
August 2004
BER Performance (DC Despreading)
Performance comparison
32-chip ~ 8-chip (3/8 bit/chip) > 16-chip
Francois Chin, Institute for Infocomm Research (I2R)

15. Range Performance Comparison (ALL)
August 2004
under Constant Transmit Power; comparison based on Ec/No at fixed chip rate
Francois Chin, Institute for Infocomm Research (I2R)

16. BER Performance (DS Despreading)
August 2004
BER Performance (DS Despreading)
Data rate vs Range trade-off – higher data rate at shorter range
Performance comparison - 32-chip > DSSS 16-chip > 16-chip > 8-chip (1/2 bit/chip)
Francois Chin, Institute for Infocomm Research (I2R)

17. BER Performance (DC Despreading)
August 2004
BER Performance (DC Despreading)
Data rate vs Range trade-off – higher data rate at shorter range
Performance comparison - 32-chip > 16-chip > 8-chip (3/8 bit/chip)
Francois Chin, Institute for Infocomm Research (I2R)

18. Summary of Code Sets Performance
August 2004
Code Set
A32
B16 C8 D8
E16
Description
32-chip
(15.4 original)
16-chip
(I2R proposed)
8-chip for DS Despreading only
8-chip
(I2R proposed)
Orthogonal 16-DSSS
Normalised RMS
X-Corr (DSD)
-17.6 dB
-14.8 dB
- 8.5 dB
-6.7 dB
Auto-Corr(DSD)
-16.0 dB
-13.0 dB
-11.5 dB
-6.0 dB
X-Corr (DCD)
-24.0 dB
N.A.
Auto-Corr (DCD)
-18.5 dB
-17.8 dB
X-Corr Spikes Abs Values (DSD)
32 (1x)
8 (8x)
4 (4x)
0 (3x)
16 (1x)
4 (8x)
0 (7x)
8 (1x)
0 (11x)
4 (6x)
0 (1x)
0 (15x)
X-Corr Spikes Values (DCD)
0 (6x)
-4 (4x)
-32 (1x)
0 (14x)
-16 (1x)
4 (2x)
0 (10x)
-4 (2x)
-8 (1x)
Francois Chin, Institute for Infocomm Research (I2R)

19. Performance Comparison - Correlation
August 2004
Performance Comparison - Correlation
The lower the cross correlation, the lower the symbol error rate
The lower the auto correlation, the better the acquisition capability
Generally, the longer the sequence length, the better the correlation properties
Trade-off better between data rate and desirable correlation properties
Francois Chin, Institute for Infocomm Research (I2R)

20. Summary of Proposal in 868 MHz
August 2004
Summary of Proposal in 868 MHz
Ch #0
868MHz band
Bandwidth
600 kHz
Recommended Code Set
8-chip code set D8 (3/8 bit/chip)
8-chip code set C8 (1/2 bit/chip)
Receiver
DS / Diff Chip Despreading
DS despreading
(low ppm reference has to be used)
Chip rate
300kcps
400kcps
500kcps
Pulse shape
Raised cosine with r=1.0
Raised cosine with r=0.5
Raised cosine with r=0.2
Modulation
BPSK
Data rate
112.5 kbps
150 kbps
187.5 kbps
200 kbps
increasing complexity
increasing data rate
Francois Chin, Institute for Infocomm Research (I2R)

21. Summary of Proposal in 915 MHz
August 2004
Ch #1-10
906 – 924 MHz band
Bandwidth
2 MHz
Recommended Code Set
16-chip code set B16 (1/4 bit/chip)
8-chip code set D8 (3/8 bit/chip)
Receiver
DS / Diff Chip Despreading
Chip rate
1Mcps
Pulse shape
Raised cosine with r=1.0
(optional - Half-sine)
Modulation
BPSK
(optional – OQPSK)
Data rate
250 kbps
375 kbps
Francois Chin, Institute for Infocomm Research (I2R)

22. August 2004
Summary
Proposed shorter mapping sequences has higher spectral efficiency (bps/Hz)
Differential chip despreading allows very inexpensive reference to be used
For 868MHz band, BPSK scheme is used. Higher data rates, from 112.5kbps – 200kbps, can be achieved using smaller raise cosine roll-off factors
For 915MHz band, with effective bandwidth of 1.5MHz, 250kbps / 375kbps can be achieved using length-16 / 8 mapping sequences respectively, together with very inexpensive reference
Uses existing modulation scheme BPSK + raise cosine pulse shaping or OQPSK + half sine pulse shaping - to maintain Low RF linearity requirement
Compared to orthogonal DSSS sequences, the length-16/8 backward compatible symbol-to-chip mapping sequences requires much lower memory requirement
Multiple modes (e.g. using 16/8 length sequences) can be incorporated into devices for flexible data rate / range performance trade-off
Francois Chin, Institute for Infocomm Research (I2R)